瑞芯微RK3506G2智能语音专用高性价比SoC芯片datasheet

RK3506G2是一款高性能的三核Cortex-A7应用处理器，专为智能语音交互、音频输入/输出处理、图像输出处理和其他数字多媒体应用而设计。嵌入式丰富的外围接口，如SAI、PDM、SPDIF、Audio DSM、Audio ADC、USB2 OTG、RMII、CAN等，可以满足不同的应用开发，降低硬件开发的复杂性和开发成本。
嵌入式2D硬件引擎和显示输出引擎，用于最大限度地减少CPU开销，以满足图像显示要求。RK3506G2具有高性能外部存储器接口，能够维持苛刻的存储器带宽。集成128MB DDR3可供客户使用。

Microprocessor

Triple-core ARM Cortex-A7 CPU
ARM architecture v7-A instruction set
ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
Include VFPv4-D32 hardware to support single and double-precision operations
Integrated 16KB L1 instruction cache, 16KB L1 data cache
128KB unified system L2 cache
TrustZone technology support
One isolated voltage domain to support DVFS

Memory Organization

Internal on-chip memory
- BootROM
- System SRAM

External off-chip memory
- SPI Nor/Nand Flash
- SDMMC(eMMC/SD Card)

Internal Memory

Internal BootRom
- Support system boot from the following device:
  - SPI Flash interface
  - SDMMC(eMMC/SD Card) interface
- Support system code download by the following interface:
  - USB OTG interface (Device mode)
  - SPI interface(Slave mode)

Internal SRAM
- 48KB System SRAM

Integrated 128MB DDR is available

External Memory or Storage device

Serial Flash Interface
- Support transfer data from/to SPI flash device
- Support x1,x2,x4 data bits mode
- Support up to 1 chip select
SD/MMC Interface
Compatible with standard iNAND interface
Compatible with eMMC specification 51
Compatible with 0, MMC ver4.51
Compatible with 0 protocol
Data bus width is 4bits

System Component

Cortex-M0
- The ARMv6-M Thumb instruction set
- Thumb-2 technology
- Nested Vectored Interrupt Controller (NVIC)
- Serial wire debug port (SW-DP) debug access

CRU (clock & reset unit)
- One oscillator with external 24MHz crystal input
- One internal low frequency RC clock
- One internal power on reset circuit
- Support single-end 768KHz clock input/output from/to GPIO
- Support PLL control and generate various clock frequency for chip
- Support clock gating control for individual components
- Support global soft-reset control for whole chip, also individual soft-reset for each component

PMU(power management unit)
- Three separate voltage domains(CPU_DVDD/LOGIC_DVDD/PMU_DVDD)
- Multiple configurable work sleep modes to save power consumption by different frequency or automatic clock gating control or external power on/off control

Timer
- Twelve 64-bit timers with interrupt-based operation
- One 64-bit timer with interrupt-based operation for low power mode application
- Support two operation modes: free-running and user-defined count
- Support timer work state checkable

PWM0
- 4-channel PWM with interrupt-based operation
- Support capture mode
- Provides reference mode and output various duty-cycle waveform
- Support continuous mode or one-shot mode
- Support one channel IR RX application
- Support four channel waveform generation through lookup table

PWM1
- 8-channels PWM with interrupt-based operation
- Support capture mode
- Provides reference mode and output various duty-cycle waveform
- Support continuous mode or one-shot mode
- Support one channel IR TX application
- Support one clock frequency calculation engine and one clock free running counter
- Support six channel biphasic counter

Watchdog
- Support two 32-bit watchdog counter
- Counter counts down from a preset value to 0 to indicate the occurrence of a timeout
- WDT can perform two types of operations when timeout occurs:
  - Generate a system reset

First generate an interrupt and if this is not cleared by the service routine by the time a second timeout occurs then generate a system reset
Programmable reset pulse length
Totally 16 defined ranges of main timeout period
Mailbox
- One Mailbox to service Cortex-A7 and Cortex-M0 communication
- Support four mailbox elements, each element includes one data word, one command word register and one flag bit that can represent one interrupt

Spinlock
- Support spinlock registers for software to realize resource management

DMA
- Support two embedded DMA controllers
- Support data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory
- Support TrustZone technology and programmable secure state for each DMA channel
- DMAC0 support 6 channels in total
- DMAC1 support 8 channels in total

Secure System
- Cipher engine
  - Support SHA-1, SHA-256/224, MD5 with hardware padding
  - Support HMAC of SHA-1, SHA-256, MD5 with hardware padding
  - Support AES-128, AES-192, AES-256 encrypt & decrypt cipher
  - Support AES ECB/CBC/OFB/CFB/CTR/CTS/XTS/CCM/GCM/CBC-MAC/CMAC mode
  - Support up to 4096 bits PKA mathematical operations for RSA
- Support two 256 bits RNG output
- Support secure boot
- Support secure debug
- Support secure OTP
- Support secure OS
- Support bus firewall

Graphics Engine

2D Graphics Engine
- SRC0 Input data format:
  - ARGB8888/RGBA8888/RGBA4444/RGBA5551
  - RGB888P/RGB565
  - YUV422-P/YUV422-SP-8bit/10bit(clip to 8bit after input)
  - YUV420-P/YUV420-SP-8bit/10bit(clip to 8bit after input)
  - YVYU422-8bit
  - YUV400-8bit
  - BPP1/2/4/8
- SRC1 Input data format:
  - ARGB8888/RGBA8888/RGBA4444/RGBA5551/A8
  - RGB888P/RGB565
- Output data format(all YUV format is 8bit):
  - ARGB8888/RGBA8888/ARGB4444/RGBA4444/ARGB5551/RGBA5551
  - RGB888/RGB565
  - YUV420/YUV422 P/SP
  - YUV400
- Pixel Format conversion, 601/BT.709
- Dither operation

Max resolution: 1280×1280 source, 1280×1280 destination
Scaling
- Down-scaling: Average filter
- Up-scaling: Bi-cubic filter(Horizontal, Vertical), Bi-linear filter(Vertical)
- Arbitrary non-integer scaling ratio, from 1/16 to 16
Rotation
- 0, 90, 180, 270 degree rotation
- x-mirror, y-mirror operation
- Mirroring and rotation co-operation
BitBLT
- Block transfer
- Color palette/Color fill, support with alpha
- Transparency mode (color keying/stencil test, specified value/value range)
- Two source BitBLT
- A+B=B only BitBLT, A support rotate & scale when B fixed
- A+B=C second source (B) has same attribute with (C) plus rotation function
Alpha Blending
- Comprehensive per-pixel alpha(color/alpha channel separately)
- Fading
- Support SRC1(R2Y)+SRC0(YUV) -> DST(YUV)
- Support DST Full CSC convert for YUV2YUV
Others
- Supports Gaussian filters with a window size of 3 * 3

Video Output Processor

Display Interface
- Support parallel MCU/RGB LCD interface: 24-bit(RGB888), 18-bit(RGB666), 16- bit(RGB565)
- Support serial MCU/RGB LCD interface: 3×8-bit(RGB888), 3×6-bit(RGB666), 2×8- bit(RGB565)
- Support 656/BT.1120 interface
- Support 2lane MIPI interface, 5Gbps/lane
- Max output resolution is 1280×1280@60fps
Display process
- Background layer
  - programmable 24-bit color
- Win1 layer
  - RGB888, ARGB888, RGB565
  - Support virtual display
  - 256 level alpha blending (pre-multiplied alpha support)
  - Transparency color key
  - RGB2YUV(BT601/BT709)
- Others
  - Support RGB or YUV domain overlay
  - BCSH (Brightness, Contrast, Saturation, Hue adjustment)
  - BCSH: RGB2YUV(BT601/BT709)
  - Support dither down allegro RGB888to666 RGB888to565 and dither down FRC(Frame Rate Control) (configurable) RGB888to666
  - Blank and black display
  - Standby mode

Audio Interface

SAI
- Support five SAI components
- Support audio protocol: I2S, PCM, TDM
- Support up to 128 slots available with configurable size
- Support slot length 8 to 32 bits configurable
- Support master and slave mode, software configurable
- Sample rate up to 192KHz
- Support slot valid data length 8 to 32 bits configurable
- SAI0 support up to one lane transmitter and four lane parallel receivers
- SAI1 support up to four lane parallel transmitters and one lane receiver
- SAI2 support up to one lane transmitter and one lane receiver
- SAI0/1/2 connected to chip GPIO
- SAI3 support up to one lane transmitter and one lane receiver
- SAI4 support up to one lane receiver
- SAI3 connected to internal Audio DSM modulator and chip GPIO optional, and SAI4 connected to internal Audio ADC
PDM
- Support PDM master receive mode
- Support 5 wire PDM interface with one is clock and 4 data line
- Support up to 8 mono microphones
- Support 16~24 bits sample resolution
- Sample rate up to 192KHz

SPDIF
- Support SPDIF TX x 1
- Support SPDIF RX x 1
- Support 16bits/20bits/24bits resolution
- Support linear PCM mode (IEC-60958)
- Support non-linear PCM transfer (IEC-61937)
- Sample rate up to 192KHz

ASRC
- Support two ASRC components
- Support fixed length conversion mode and real time conversion mode
- Support asynchronous sample rate clock for real time conversion mode
- Support 4 channel sample rate converter for each ASRC
- Support combine two ASRC component to meet 8 channel sample rate converter

Audio DSM
- Support 2-channel digital DAC
- Support I2S/PCM master and slave mode
- Support 16 bit sample resolution
- Support volume control
- Sample rate up to 192KHz

Audio ADC
- One channel 24 bit ADC microphone input
- Support one differential microphone input
- Support I2S as the digital signal interface
- Support both master and slave mode
- Support 16bits/24bits resolution
- Support I2S normal, left and right justified mode
- Sample rate up to 192KHz

Connectivity

RMII 10/100 Ethernet Controller
- Support two Ethernet Controllers
- Supports 10/100-Mbps data transfer rates with the RMII interfaces
- Supports both full-duplex and half-duplex operation
USB 0 OTG
Support two USB 0 OTG ports
Compatible with USB 0 specification
Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
DSMC master interface
- Support master role
- Support transfer data from/to Xccela pSRAM device
- Support transfer data from/to Hyperbus pSRAM device
- Support act as local bus to transfer data from/to another device with DSMC slave interface
- Support x8,x16 data bits mode
- Support DDR mode

DSMC slave interface
- Support slave role
- Support act as local bus to transfer data from/to another device with DSMC master interface
- Support x8 data bits mode
- Support DDR mode

FLEXBUS interface
- Support transfer data from internal memory to GPIO by DMA
- Support transfer data from GPIO to internal memory by DMA
- Support multiple operating modes
  - Multiplexing TX clock and RX clock, Multiplexing TX data and RX data
    - Support TX only mode, RX only mode, TX then RX mode
  - Multiplexing TX clock and RX clock, Separating TX data and RX data
    - Support TX only mode, RX only mode, TX and RX mode, TX then RX mode
  - Separating TX clock and RX clock, Separating TX data and RX data
    - Support TX only mode, RX only mode, TX and RX mode
  - Support clock free running mode and following data mode
  - Support TX data width 1, 2, 4, 8, 16 bit configurable
  - Support RX data width 1, 2, 4, 8, 16 bit configurable
  - Support continue transmission mode and fix length transmission mode
  - Support one chip selection function for multiplexing TX clock and RX clock mode
  - Support two chip selection function for separating TX clock and RX clock mode, one for TX direction, the other for RX direction
  - Support TX clock auto gating
  - Support DVP (RGB888, RGB565, YUV422) interface for camera sensor

SPI interface
- Support three SPI Controllers
- SPI0/SPI1 support serial-master and serial-slave mode, software-configurable
- Support 2 chip-selects output in serial-master mode
- SPI2 support serial-slave mode

I2C interface
- Support three I2C interface
- Support 7bits and 10bits address mode
- Software programmable clock frequency
- Data on the I2C-bus can be transferred at rates of up to 100 Kbit/s in the Standard-mode, up to 400 Kbit/s in the Fast-mode or up to 1 Mbit/s in Fast-mode Plus

UART Controller
- Support six UART interface
- Embedded two 64-byte FIFO for TX and RX operation respectively

- Support 5bit, 6bit, 7bit, 8bit serial data transmit or receive
- Standard asynchronous communication bits such as start, stop and parity
- Support different input clock for UART operation to get up to 4Mbps baud rate
- Support auto flow control mode

CAN Controller
- Support two CAN interface
- Support CAN 0B protocol
- Support transmit or receive standard frame
- Support transmit or receive extended frame

Touch Key Controller
- Support muti-channel CapSense monitor
- Support trigger interrupt waterline configurable
- Support LPF and DC elimination

Others

Multiple groups of GPIO
- All of GPIOs can be used to generate interrupt
- Support level trigger and edge trigger interrupt
- Support configurable polarity of level trigger interrupt
- Support configurable rising edge, falling edge and both edge trigger interrupt
- Support configurable pull direction (pullup or pulldown)
- Support configurable drive strength
- Support configurable slew rate