君正 X1000/E 是一款低功耗、高性能、高集成度的通用SoC，采用MIPS XBurst处理器，其应用主要集中在物联网设备上，可以满足许多嵌入式产品的要求。
X1000/E Diagram
1.2 Features
1.2.1 CPU Core
MIPS-Based XBurst® cores (up to 1.0GHz)
MIPS-Based XBurst® CPU
– XBurst® RISC instruction set
– XBurst® SIMD instruction set
– XBurst® FPU instruction set supporting both single and double floating point format
X1000 IoT Application Processor DataSheet
which are IEEE754 compatible
– XBurst® 9-stage pipeline micro-architecture
MMU
– 32-entry joint-TLB
– 4 entry Instruction TLB
– 4 entry data TLB
L1 Cache
– 16KB instruction cache
– 16KB data cache
Hardware debug support
16KB tight coupled memory
L2 Cache
– 128KB unify cache
The XBurst® processor system supports little endian only
1.2.2 Image Core
Hardware JPEG encoder
– Baseline ISO/IEC 10918-1 JPEG compliant
– 8-bit pixel depth support
– Support for YUY2 ([Y0,U0,Y1,V0]) color
– Up to four programmable Quantization tables
– Fully programmable Huffman tables
– Image size up to 2M pixels
1.2.3 Display/Camera/Audio
LCD controller
– Basic Features
Display size up to 640×480@60Hz,24BPP
– Colors Supports
Support up to 16,777,216 (16M) colors
– Panel Supports
16bit 8080 once parallel interface
9 bits twice 8080 parallel interface
8 bits twice/third times 8080 parallel
Supports different size of display panel
Supports internal DMA operation and register operation
Camera interface module
– Input image size up to 2M pixels
– Integrated DMA
– Supported data format: YCbCr 4:2:2
– Supports ITU656 (YCbCr 4:2:2) input
X1000 IoT Application Processor DataSheet
– Configurable VSYNC and HSYNC signals: active high/low
– Configurable PCLK: active edge rising/falling
– PCLK max. 80MHz
– Configurable output order
AIC controller
– I2S features
8, 16, 18, 20 and 24 bit audio sample data sizes supported, 16 bits packed sample data is supported
Up to 8 channels sample data supported
DMA transfer mode supported
Stop serial clock supported
Programmable Interrupt function supported
Support share clock mode and split clock mode.
Support mono PCM data to stereo PCM data expansion on audio play back
Support endian switch on 16-bits normal audio samples play back
Internal programmable or external serial clock and optional system clock supported for I2S or MSB-Justified format
Internal I2S CODEC supported
Two FIFOs for transmit and receive respectively
PCM interface
– Support master mode and slave mode
– Data starts with the frame PCMSYN or one PCMCLK later
– Support three modes of operation for PCM
Short frame sync mode
Long frame sync mode
Multi-slot mode
– Data is transferred and received with the MSB first
– The PCM serial output data, PCMDOUT, is clocked out using the rising edge of the PCMSCLK
– The PCM serial input data, PCMDIN, is clocked in on the falling edge of the PCMSCLK
– 8/16 bit sample data sizes supported
– DMA transfer mode supported
– Two FIFOs for transmit and receive respectively with 16 samples capacity in every direction
Internal CODEC
– 24 bits ADC and DAC(digital output)
– PWM line out and can load down to 16 Ohm
– Sample rate supported: 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k, 88.2k, 96k, 176.4k, and 192k
– Mono line input
– DAC(digital output and converter to analog by external circuit): SNR: 95dB A-Weighted, THD: -80dB @FS-1dB
– Line input to ADC path: SNR: 90dB A-Weighted, THD: -80dB @FS-1dB
X1000 IoT Application Processor DataSheet
– Separate power-down modes for ADC and DAC path with several shutdown modes
– Reduction of audible glitches systems: Soft Mute mode
– Embedded low noise Linear Regulator
– 1 MIC in path or 1 line in path Maximum (Total 1 analog input)
Low power DMIC Controller
– 16 bits data interface and 20bit precision internal controller.
– SNR: 90dB, THD: -90dB @ FS -20dB
– Linear high pass filter include. Attenuation: -2.9dB@100Hz, -22dB@27Hz. -36dB@10Hz
– Low power voice trigger when waiting to start talking.
– 1 to 4 channel MIC support.
– Support voice data pre-fetch when trigger enable and the data interface disable, but do not increase the power dissipation.
– Sample rate supported: 8k, 16k.
– Support low power mode
1.2.4 Memory Interface
DDR Controller
– Support LPDDR, DDR2, DDR3
– 16 bit data width
– Support size up to 1GB (1 chip select, 3-bit Bank,15-bit Row, 11-bit Column,)
– Asynchornize to system bus and each port.
– Support clock-stop mode
– Support auto self-refresh mode
– Support power-down mode and deep-power-down mode
– Programmable DDR timing parameters
– Programmable DDR row and column address width and order
X1000: 32MB SIP LPDDR
X1000E: 64MB SIP LPDDR
Serial nand/nor flash interface(SFC)
– SPI protocol support: Standard, Dual, Quad SPI
– Standard I/O data transfer up to 80Mbits/s
– Dual I/O data transfer up to 160Mbits/s
– Quad I/O data transfer up to 240Mbits/s
– transmit-only or receive-only operation
– MSB always be first in intra transfer of one byte. Least Significant Byte first for inter transfer of data bytes, and Most Significant Byte first for inter transfer of command or address bytes.
– one device select
– Configurable sampling point for reception
– Configurable timing parameters: tSLCH, tCHSH and tSHSL
– Configurable flash address wide are supported
X1000 IoT Application Processor Data Sheet
– 7 transfer formats: Standard SPI, Dual-Output/Dual-Input SPI, Quad-Output/Quad-Input SPI, Dual-I/O SPI, Quad-I/O SPI, Full Dual-I/O SPI, Full Quad-I/O SPI
– two data transfer mode: slave mode and DMA mode
– Configurable 6 phases for software flow
1.2.5 System Functions
Clock generation and power management
– On-chip oscillator circuit (support 24MHz, 26MHz)
– Two phase-locked loops (PLL) with programmable multiplier
– CCLK, HHCLK, H2CLK, PCLK, H0CLK, DDR_CLK frequency can be changed separately for software by setting registers
– Functional-unit clock gating
– Supply block power shut down
Timer and counter unit with PWM output and/or input edge counter
– Provide 5 channels, all can generate PWM, two of them have input signal transition edge counter
– 16-bit A counter and 16-bit B counter with auto-reload function every channel
– Support interrupt generation when the A counter underflows
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
OS timer
– One channel
– 32-bit counter and 32-bit compare register
– Support interrupt generation when the counter matches the compare register
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
Interrupt controller
– Total 64 interrupt sources
– Each interrupt source can be independently enabled
– Priority mechanism to indicate highest priority interrupt
– All the registers are accessed by CPU and PDMA
– Unmasked interrupts can wake up the chip in sleep mode
– Another set of source, mask and pending registers to serve for PDMA
Watchdog timer
– Generates WDT reset
– A 16-bit Data register and a 16-bit counter
– Counter clock uses the input clock selected by software
PCLK, EXTAL and RTCCLK can be used as the clock for counter
X1000 IoT Application Processor Data Sheet
The division ratio of the clock can be set to 1, 4, 16, 64, 256 and 1024 by software
PDMA Controller
– Support up to 8 independent DMA channels
– Descriptor or No-Descriptor Transfer mode
– A simple Xburst®-1 CPU supports smart transfer mode controlled by programmable firmware
– Transfer data units: 1-byte, 2-byte, 4-byte, 16-byte, 32-byte, 64-byte, 128-byte
– Transfer number of data unit: 1 ~ 224 – 1
– Independent source and destination port width: 8-bit, 16-bit, 32-bit
– Fixed three priorities of channel groups: 0~3, highest; 4~11: mid; 12~31: lowest
– An extra INTC IRQ can be bound to one programmable DMA channel
RTC (Real Time Clock)
– Need external 32768Hz oscillator for 32KHz clock generation.
– RTCLK selectable from the oscillator or from the divided clock of EXCLK, so that 32k crystal can be absent if the hibernating mode is not needed
– 32-bits second counter
– Programmable and adjustable counter to generate accurate 1 Hz clock
– Alarm interrupt, 1Hz interrupt
– Stand alone power supply, work in hibernating mode
– Power down controller
– Alarm wakeup
– External pin wakeup with up to 2s glitch filter
1.2.6 Peripherals
General-Purpose I/O ports
– Each port can be configured as an input, an output or an alternate function port
– Each port can be configured as an interrupt source of low/high level or rising/falling edge triggering. Every interrupt source can be masked independently
– Each port has an internal pull-up or pull-down resistor connected. The pull-up/down resistor can be disabled
– GPIO output 4 interrupts, 1 for every group, to INTC
Three I2C Controller (I2C0, I2C1, I2C2)
– Two-wire I2C serial interface – consists of a serial data line (SDA) and a serial clock (SCL)
– Two speeds
Standard mode (100 Kb/s)
Fast mode (400 Kb/s)
– Device clock is identical with pclk
– Programmable SCL generator
X1000 IoT Application Processor DataSheet
– Master or slave I2C operation
– 7-bit addressing/10-bit addressing
– -level transmit and receive FIFOs
– Interrupt operation
– The number of devices that you can connect to the same I2C-bus is limited only by the maximum bus capacitance of 400pF
One Smart Card Controller (SCC)
– Supports normal card and UIM card.
– Supports asynchronous character (T=0) communication modes.
– Supports asynchronous block (T=1) communication modes.
– Supports setting of clock-rate conversion factor F (372, 512, 558, etc.), and bit-rate adjustment factor D (1, 2, 4, 8, 16, 32, 12, 20, etc.).
– Supports extra guard time waiting.
– Auto-error detection in T=0 receive mode.
– Auto-character repeat in T=0 transmit mode.
– Transforms inverted format to regular format and vice versa.
– Support stop clock function in some power consuming sensitive applications.
One Synchronous serial interfaces (SSI0)
– 3 protocols support: National’s Microwire, TI’s SSP, and Motorola’s SPI
– Full-duplex or transmit-only or receive-only operation
– Programmable transfer order: MSB first or LSB first
– Configurable normal transfer mode or Interval transfer mode
– Programmable clock phase and polarity for Motorola’s SSI format
– Two slave select signal (SSI0_CE0_ / SSI0_CE1_) supporting up to 2 slave devices
– Back-to-back character transmission/reception mode
– Loop back mode for testing
– Data transfer up to 30Mbits/s
Three UARTs (UART0, UART1, UART2)
– Full-duplex operation
– 5-, 6-, 7- or 8-bit characters with optional no parity or even or odd parity and with 1, 1½, or 2 stop bits
– Independently controlled transmit, receive (data ready or timeout), line status interrupts
– Internal diagnostic capability Loopback control and break, parity, overrun and framing-error is provided
– Separate DMA requests for transmit and receive data services in FIFO mode
– Supports modem flow control by software or hardware
– Slow infrared asynchronous interface that conforms to IrDA specification
Two MMC/SD/SDIO controllers (MSC0, MSC1)
– Fully compatible with the MMC System Specification version 4.5
– Support SD Specification 3.0
– Support SD I/O Specification 1.0 with 1 command channel and 4 data channels
– Consumer Electronics Advanced Transport Architecture (CE-ATA – version 1.1)
– Maximum data rate is 50MBps
– Both support MMC data width 1bit ,4bit, only MSC0 support 8bit
– Built-in programmable frequency divider for MMC/SD bus
– Built-in Special Descriptor DMA
– Mask-able hardware interrupt for SDIO interrupt, internal status and FIFO status
– Multi-SD function support including multiple I/O and combined I/O and memory
– IRQ supported enable card to interrupt MMC/SD controller
– Single or multi block access to the card including erase operation
– Stream access to the MMC card
– Supports SDIO read wait, interrupt detection during 1-bit or 4-bit access
– Supports CE-ATA digital protocol commands
– Support Command Completion Signal and interrupt to CPU
– Command Completion Signal disable feature
– The maximum block length is 4096bytes
USB 2.0 OTG interface
– Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and with the On-The-Go supplement to the USB 2.0 specification
– Operates either as the function controller of a high- /full-speed USB peripheral or as the host/peripheral in point-to-point or multi-point communications with other USB functions
– Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
– UTMI+ Level 3 Transceiver Interface
– Soft connect/disconnect
– 8 endpoints in device mode, 16 channels for host mode.
– Dedicate FIFO
– Supports control, interrupt, ISO and bulk transfer
MAC controller
– 10/100 Mbps operation
– Supports RMII PHY interfaces
– Supports VLAN and CRC
– Station Management Agent (SMA)
– remote wake-up frame and magic packet frame processing
OTP Slave Interface
– Total 1Kb.
1.2.7 Bootrom
16KB Boot ROM memory
X1000 IoT Application Processor DataSheet
