瑞芯微RK3562J芯片详细规格参数Datasheet

RK3562J是一款专为消费类电子设备设计的高性能、低功耗四核应用处理器。RK3562J具有多个嵌入式硬件引擎，可优化高端应用程序的性能。它支持几乎全格式的H.264解码1080p@60fps，H.265解码4K@30fps，和H.264编码1080p@60fps.此外，它还包括一个高质量的JPEG编码器和解码器。

RK3562J包含嵌入式3D GPU，可确保与OpenGL ES 1.1/2.0/3.2、OpenCL 2.0和Vulkan 1.1完全兼容。此外，还包括一个特殊的2D硬件引擎，以最大限度地提高显示性能并确保平稳运行。RK3562J具有高性能外部存储器接口（DDR3/DDR3L/DDR4/LPDDR3/LPDDR4/LPDDR4X），能够维持苛刻的存储器带宽。

1.2.1 Microprocessor
 Quad-core ARM Cortex-A53 MPCore processor, high-performance, low-power and cached application processor
 Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
 ARMv8 Cryptography Extensions
 In-order pipeline with symmetric dual-issue of most instructions.
 Integrated 32KB L1 instruction cache, 32KB L1 data cache with 4-way set associative
 Level 2 (L2) memory system providing cluster memory coherency, including an L2 cache.
 Include VFP v3 hardware to support single and double-precision add, subtract, divide, multiply and accumulate, and square root operations
 TrustZone technology support
 Separate power domains for CPU core system to support internal power switch and externally turn on/off based on different application scenarios
 PD_A53_0: 1st Cortex-A53 + Neon + FPU + L1 I/D Cache
 PD_A53_1: 2nd Cortex-A53 + Neon + FPU + L1 I/D Cache
 PD_A53_2: 3rd Cortex-A53 + Neon + FPU + L1 I/D Cache
 PD_A53_3: 4th Cortex-A53 + Neon + FPU + L1 I/D Cache
 One isolated voltage domain
1.2.2 Memory Organization
 Internal on-chip memory
 BootROM
 Support system boot from the following device:
 SPI Flash interface
 eMMC interface
 SDMMC interface
 Support system code download by the following interface:
 USB OTG interface (Device mode)
 Internal SRAM
 External off-chip memory
 Dynamic Memory Interface
 Compatible with JEDEC standards① DDR3-2133/DDR3L-2133/LPDDR3-2133/DDR4-2666/LPDDR4-2666/LPDDR4X-2666
 Support 32bits data width, 2 ranks (chip selects), total addressing space is 8GB(max) for DDR3/DDR3L/DDR4
 Support 32bits data width, 4 ranks (chip selects), total addressing space is 8GB(max) for LPDDR3/LPDDR4/LPDDR4X
 Low power modes, such as power-down and self-refresh for SDRAM
 Compensation for board delays and variable latencies through programmable pipelines
 Programmable output and ODT impedance with dynamic PVT compensation
 eMMC Interface
 Compatible with standard iNAND interface
 Compatible with eMMC specification 4.41, 4.51, 5.0 and 5.1
 Support three data bus width: 1bit, 4bits or 8bits
 Support up to HS200 and HS400;
 Support CMD Queue
 SD/MMC Interface
 Compatible with SD3.0, MMC ver4.51
 Data bus width is 4bits
 Flexible Serial Flash Interface(FSPI)
 Support transfer data from/to serial flash device
 Support 1bit/2bit/4bit data bus width
 Support 2 chip select
1.2.3 System Component
 CRU (clock & reset unit)
 Support total 6 PLLs to generate all clocks
 One oscillator with 24MHz clock input
 Support clock gating control for individual components
 Support global soft-reset control for whole chip, also individual soft-reset for each component
 MCU
 Two MCUs inside RK3562J
 One in VD_LOGIC integrate 16KB Cache
 One in VD_PMU
 Integrated Programmable Interrupt Controller (IPIC), all IRQ lines connected to GIC for CPU also connect to MCU in VD_LOGIC
 Integrated Debug Controller with JTAG interface
 PMU(power management unit)
 Multiple configurable work modes to save power by different frequency or automatic clock gating control or power domain on/off control
 Lots of wakeup sources in different modes
 Support 5 separate voltage domains
 Support 13 separate power domains, which can be power up/down by software based on different application scenes
 Timer
 Six 64bits timers with interrupt-based operation for non-secure application
 Two 64bits timers with interrupt-based operation for secure application
 Support two operation modes: free-running and user-defined count
 Support timer work state checkable
 Watchdog
 32bits watchdog counter
 Counter counts down from a preset value to 0 to indicate the occurrence of a timeout
 WDT can perform two types of operations when timeout occurs:
 Generate a system reset
 First generate an interrupt and if this is not cleared by the service routine by the time a second timeout occurs then generate a system reset
 Totally 3 Watchdog for CPU and MCU
 Interrupt Controller
 Support 3 PPI interrupt sources and 256 SPI interrupt sources input from different components
 Support 16 software-triggered interrupts
 Two interrupt outputs (nFIQ and nIRQ) separately for each Cortex-A53, both are low-level sensitive
 Support different interrupt priority for each interrupt source, and they are always software-programmable
 Mailbox
 Two Mailbox in SoC to service Cortex-A53 and MCU communication
 Support four mailbox elements per mailbox, each element includes one data word, one command word register and one flag bit that can represent one interrupt
 Provide 32 lock registers for software to use to indicate whether mailbox is occupied
 DMAC
 Micro-code programming based DMA
 Linked list DMA function is supported to complete scatter-gather transfer
 Support data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory
 One embedded DMA controller for system
 DMAC features:
 8 channels totally
 32 hardware request from peripherals
 2 interrupt outputs
 Secure System
 Embedded two Cipher engine
 Support Link List Item (LLI) DMA transfer
 Support SHA-1, SHA-256/224, MD5 with hardware padding
 Support HMAC of SHA-1, SHA-256, MD5 with hardware padding
 Support AES-128, AES-192, AES-256 cipher
 Support DES & TDES cipher
 Support AES ECB/CBC/OFB/CFB/CTR/CTS/XTS/CCM/GCM/CBC-MAC/CMAC mode
 Support DES/TDES ECB/CBC/OFB/CFB mode
 Support up to 4096 bits PKA mathematical operations for RSA
 Support generating random numbers
 Support keyladder to guarantee key secure
 Support data scrambling for all DDR types
 Support secure OTP
 Support secure debug
 Support secure OS
 Except CPU, the other masters in the SoC can also support security and non-security mode by software-programmable
 Some slave components in SoC can only be addressed by security master and the other slave components can be addressed by security master or non-security master by software-programmable
 System SRAM, part of space is addressed only in security mode
 External DDR space can be divided into 16 parts; each part can be software-programmable to be enabled by each master
1.2.4 Video CODEC
 Video Decoder
 H.265 HEVC/MVC Main Profile yuv420@L5.0 up to 4096×2304@30fps
 H.264 AVC/MVC Main Profile yuv400/yuv420/yuv422/@L5.0 up to 1920×1080@60fps
 VP9 Profile0 yuv420@L5.0 up to 4096×2304@30fps
 Video Encoder
 H.264 High Profile level4.2, up to 1920×1080@60fps
 Support YUV/RGB video source with rotation and mirror
RK3562J Datasheet Rev 1.0 BY SCENSMART
1.2.5 JPEG CODEC
 JPEG decoder
 48×48 to 65536×65536(4295Mpixels), Step size 8 pixels
 Baseline interleaved, and support DRI decode
 JPEG encoder
 Baseline Non-progressive
 up to 8192×8192
 up to 90 million pixels per second
1.2.6 Graphics Engine
 3D Graphics Engine:
 Mali-G52 1-Core-2EE
 Support OpenGL ES 1.1, 2.0, and 3.2
 Support Vulkan 1.0 and 1.1
 Support OpenCL 2.0 Full Profile
 Support 1600Mpix/s fill rate when 800MHz clock frequency
 Support 38.4 FP32 GFLOPs when 800MHz clock frequency
 2D Graphics Engine:
 Data format
 Support input of ARGB/RGB888/RGB565/RGB4444/RGB5551/YUV420/YUV422/YUYV；；
 Support input of YUV422SP10bit/YUV420SP10bit(YUV-8bits out)
 Support output of ARGB/RGB888/RGB565/RGB4444/RGB5551/YUV420/YUV422/YUYV；；
 Pixel Format conversion, BT.601/BT.709
 Dither operation, Y dither update;
 Max resolution: 8192×8192 source, 4096×4096 destination
 Scaling
 Down-scaling: Average filter
 Up-scaling: Bi-cubic filter(source>2048 would use Bi-linear)
 Arbitrary non-integer scaling ratio，，from 1/16 to 16
 Rotation
 0, 90, 180, 270 degree rotation
 x-mirror, y-mirror& rotation operation
 BitBLT
 Block transfer
 Color palette/Color fill, support with alpha
 Transparency mode (color keying/stencil test, specified value/value range)
 Two source BitBLT:
 A+B=B only BitBLT, A support rotate&scale when B fixed
 A+B=C second source (B) has same attribute with (C) plus rotation function
 Alpha Blending
 New comprehensive per-pixel alpha(color/alpha channel separately)
 Fading
 SRC1(R2Y)&&SRC0(YUV)——alpha->DST(YUV)
 OSD Automatic Inversion
 Supports OSD sources in ARGB8888/ARGB1555/ARGB444/ARGB2BPP format
 Support SRC0 and OSD overlay
1.2.7 Video input interface
 Interface and video input processor
 Support MIPI CSI RX interface
 Support VICAP block(Video Input Processor)
 Support video data from MIPI CSI
 Support ISP block(Image Signal Processor)
 MIPI CSI RX Interface
 Compatible with the MIPI Alliance Interface specification v1.2
 Up to 4 data lanes, 2.5Gbps maximum data rate per lane
 Support MIPI-HS, MIPI-LP mode
RK3562J Datasheet Rev 1.0 BY SCENSMART
 Support two mode
 One interface with 1 clock lane and 4 data lanes
 Two interface, each with 1 clock lane and 2 data lanes
 VICAP
 Support receiving four interfaces of MIPI CSI/DSI, up to four IDs for each interface
 Support VC/DT configurable for each ID
 Support five CSI data formats: RAW8/10/12/14, YUV422
 Support YUYV input sequence configurable and YUYV sequence reorder
 Support three modes of MIPI CSI HDR: virtual channel mode, identification code mode, line counter mode
 Support one DSI data formats: RGB888, support video mode/command mode
 Support reducing frame rate
 Support window cropping
 Support sending RAW data directly to ISP
 Support 8/16/32 times down-sampling for RAW data
 Support virtual stride when write to DDR
 Support NV16/NV12/YUV400/YUYV output format for YUV data
 Support compact/non-compact output format for RAW data
 ISP
 VICAP input: RX raw8/raw10/raw12
 3A: Include Auto Enhance (AE)/Histogram, Auto Focus (AF), and Auto White Balance (AWB) statistics output
 BLC: Black Level Correction
 DPCC: Static/Dynamic Defect Pixel Cluster Correction
 PDAF: Phase Detection Auto Focus
 LSC: Lens Shading Correction
 Bayer-3DNR: Temporal Bayer-raw Noise Reduction
 HDR-MGE: 2-Frame Merge into High-Dynamic Range
 HDR-DRC: HDR Dynamic Range Compression, Tone mapping
 DeBayer: Advanced Adaptive Demosaic
 CCM/CSM: Color Correction Matrix, RGB2YUV, etc.
 Gamma: Gamma out correction
 Dehaze/Enhance: Automatic Dehaze and effect enhancement
 3DLUT: 3D-LUT Color Palette for Customer
 LDCH: Lens Distortion Correction only in the Horizontal direction
 YUV-2DNR: Spatial YUV Noise Reduction
 Sharp: Image sharpening and boundary filtering
 Gain: Image local gain
 Multi-sensor reuse ISP, 4 sensors for maximum
 Maximum resolution is 4224×3136, throughput 13M @30fps
1.2.8 Display interface
 Display interface
 Support RGB Parallel Display interface
 Support BT656/BT1120 interface
 Support MIPI_DSI interface
 Support LVDS interface
 RGB video output interface
 Support up to 2048×1080@60Hz
 Support RGB(up to 8bit) format
 Up to 150MHz data rate
 BT.656/BT.1120 video output interface
 BT1120 up to 1080 P/I output
 BT656 up to 576 P/I output
 MIPI DSI TX interface
 Compatible with MIPI Alliance Interface specification v1.2
 Support 1 channel DSI
 Support 4 data lanes per channel
RK3562J Datasheet Rev 1.0 BY SCENSMART
 Support 1.2Gbps maximum data rate per lane
 Up to 2048×1080@60Hz display output
 Support RGB(up to 8bit) format
 LVDS interface
 Compliant with the TIA/EIA-644-A LVDS specification
 Support RGB888 and RGB666 input for LVDS interface
 Support VESA/JEIDA LVDS data format transfer
 Up to 800×1280@60Hz display output
1.2.9 Video Output Processor
 Video input
 Support 4 Esmart layer
 Support up to 3840×2160 input resolution
 Support RGB/YUV/YUYV format
 Support scale up/down ratio 8~1/8
 Support 4 regions
 Overlay
 Support MAX 4 layers overlay
 Support RGB/YUV domain overlay
 Post process
 3D-LUT/P2I/CSC/BCSH/DITHER/GAMMA/COLORBAR
 Write back
 Format: XRGB8888/RGB888/RGB565/YUV420
 Max resolution: 1920×1080
 Video output
 Video output, up to 2048×1080@60Hz resolution
1.2.10 Audio Interface
 SAI(Serial Audio Interface)
 Support audio protocol: I2S, PCM, TDM
 Support 3 SAI controllers
 Up to 4 lanes TX and 4 lanes RX path for SAI0/SAI1
 Up to 1 lanes TX and 1 lanes RX path for SAI2
 Audio resolution from 8bits to 32bits
 Sample rate up to 192KHz
 Provides master and slave work mode, software configurable
 Support 3 I2S formats (normal, left-justified, right-justified)
 Support 4 PCM formats (early, late1, late2, late3)
 Support TDM normal, 1/2 cycle left shift, 1 cycle left shift, 2 cycle left shift, right shift mode serial audio data transfer
 I2S, PCM and TDM mode cannot be used at the same time
 SPDIF
 Support two 16-bit audio data store together in one 32-bit wide location
 Support biphase format stereo audio data output
 Support 16 to 31 bit audio data left or right justified in 32-bit wide sample data buffer
 Support 16, 20, 24 bits audio data transfer in linear PCM mode
 Support non-linear PCM transfer
 PDM
 Up to 8 channels
 Audio resolution from 16bits to 24bits
 Sample rate up to 192KHz
 Support PDM master receive mode
 Digital Audio Codec
 Support 2-channel digital DAC
 Support I2S/PCM interface
 Support I2S/PCM master and slave mode
 Support 2-channel audio receiving in I2S mode
 Support 2-channel audio receiving in PCM mode
RK3562J Datasheet Rev 1.0 BY SCENSMART
 Support I2S normal, left and right justified mode serial audio data transfer
 Support PCM early, late1, late2, late3 mode serial audio data transfer
 Support MSB or LSB first serial audio data transfer
 Support configurable SCLK and LRCK polarity
 Support 16 bit sample resolution
 Support programmable left and right channel exchangeable in I2S mode and PCM mode
 Support three modes of mixing for every digital DAC channel
 Support volume control
 Support programmable negative and positive volume gain
1.2.11 Connectivity
 SDIO interface
 Compatible with SDIO3.0 protocol
 4bits data bus widths
 MAC 10/100 Ethernet Controller
 Support 10/100 Mbps data transfer rates with the RMII interfaces
 Support both full-duplex and half-duplex operation
 GMAC 10/100/1000 Ethernet Controller
 Support 10/100/1000 Mbps data transfer rates with the RGMII interfaces
 Support 10/100 Mbps data transfer rates with the RMII interfaces
 Support both full-duplex and half-duplex operation
 USB 2.0 Host
 Support one USB2.0 Host
 Compatible with USB 2.0 specification
 Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
 Support Enhanced Host Controller Interface Specification (EHCI), Revision 1.0
 Support Open Host Controller Interface Specification (OHCI), Revision 1.0a
 Multi-PHY Interface
 Support multi-PHY with one PCIe2.1 and one USB3.0 controller
 support one of the following interfaces
 USB3.0 Host
 PCIe2.1
 USB 3.0 Dual-Role Device (DRD) Controller
 Static USB3.0 Device
 Static USB3.0 xHCI host
 USB3.0/USB2.0 OTG A device and B device basing on ID
 PCIe2.1 interface
 Compatible with PCI Express Base Specification Revision 2.1
 Support one lane
 Support Root Complex(RC) mode only
 Support 2.5Gbps and 5.0Gbps serial data transmission rate per lane per direction
 SPI interface
 Support 3 SPI Controller
 Support two chip-select output
 Support serial-master and serial-slave mode, software-configurable
 I2C interface
 Support 6 I2C Master
 Support 7bits and 10bits address mode
 Software programmable clock frequency
 Data on the I2C-bus can be transferred at rates of up to 100Kbit/s in the Standard-mode, up to 400Kbit/s in the Fast-mode.
 UART Controller
 Support 10 UART interfaces
 Embedded two 64-byte FIFO for TX and RX operation respectively
 Support 5bits,6bits,7bits,8bits serial data transmit or receive
 Standard asynchronous communication bits such as start, stop and parity
RK3562J Datasheet Rev 1.0 BY SCENSMART
 Support different input clock for UART operation to get up to 4Mbps baud rate
 Support auto flow control mode except for UART0
 PWM
 Support 16 on-chip PWMs(PWM0~PWM15) with interrupt-based operation
 Programmable pre-scaled operation to bus clock and then further scaled
 Embedded 32bits timer/counter facility
 Support capture mode
 Support continuous mode or one-shot mode
 Provides reference mode and output various duty-cycle waveform
 Optimized for IR application for PWM3, PWM7, PWM11 and PWM15
 CAN Bus
 Support 2 CAN buses
 Support CAN 2.0B protocol
 Support transmit or receive CAN standard frame
 Support transmit or receive CAN extended frame
 Support transmit or receive data frame, remote frame, overload frame, error frame and frame interval
 Compatible with ISO 11898-1-2003 specification
 Support up to 8 byte data frame
 Data rate up to 1Mbps
1.2.12 Others
 Multiple group of GPIO
 All of GPIOs can be used to generate interrupt to CPU
 Support level trigger and edge trigger interrupt
 Support configurable polarity of level trigger interrupt
 Support configurable rising edge, falling edge and both edge trigger interrupt
 Support configurable pull direction(a weak pull-up and a weak pull-down)
 Support configurable drive strength
 Temperature Sensor(TSADC)
 Up to 50KS/s sampling rate
 Support two temperature sensor
 -20~120°C temperature range and 5°C temperature resolution
 Successive Approximation ADC (SARADC)
 10bits resolution
 Up to 1MS/s sampling rate
 16 single-ended input channels
 OTP
 Support 8K bits Size, 7K bits for secure application
 Support Program/Read/Idle mode
 Package Type
 FCCSP478L (body: 13.9mm x 13.9mm; ball size: 0.3mm; ball pitch: 0.5mm&0.65mm)

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