瑞芯微RK3126芯片简介

瑞芯微RK3126芯片简介

RK3126C is a high performance Quad-core application processor for tablet. It is a high- integration and cost efficient SOC.

Quad-core Cortex-A7 is integrated with separately Neon and FPU, and shared 256KB L2 Cache. Mali400 MP2 GPU is embedded to support smoothly high-resolution display and mainstream game. Lots of high-performance interface to get very flexible solution, 16bits DDR3 provides high memory bandwidths for high-performance.

1.1  Features

• Microprocessor

• Quad-core ARM Cortex-A7MPCore processor, a high-performance, low-power and cached application processor
• Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
• Separately Integrated Neon and FPU per CPU
• 32KB/32KB L1 ICache/DCache per CPU
• Unified 256KB L2 Cache

 

• Memory Organization

• Internal on-chip memory
  • BootRom
  • Internal SRAM
• External off-chip memory
  • DDR3/ DDR3L
  • Async/Toggle/Sync Nand Flash(include LBA Nand)

• Internal Memory

• Internal BootRom
  • Size : 16KB
  • Support system boot from the following device :
    • 8bits Async Nand Flash
    • 8bits toggle Nand Flash
    • SPI interface
    • eMMC interface
    • SDMMC interface
  • Support system code download by the following interface:
    • USB OTG interface
  • Internal SRAM
    • Size : 8KB
    • Support security and non-security access
    • Security or non-security space is software programmable

• External Memory or Storage device

• Dynamic Memory Interface (DDR3/DDR3L)
  • Compatible with JEDEC standard DDR3/DDR3L SDRAM Supports DDR3-800/DDR3L-800
• Supports 16Bits data width totally 2GB (max) address
• 7 host ports with 64bits/128bits AXI bus interface for system access, AXI bus clock is asynchronous with DDR clock
• Programmable timing parameters to support DDR3/DDR3L SDRAM from various vendor
• Advanced command reordering and scheduling to maximize bus utilization
• Low power modes, such as power-down and self-refresh for DDR3/DDR3L SDRAM; Compensation for board delays and variable latencies through programmable pipelines
• Programmable output and ODT impedance with dynamic PVT compensation
• Nand Flash Interface
  • Support 8bits async/toggle/sync nandflash, up to 4 banks
  • Support LBA nandflash
  • 16bits, 24bits, 40bits, 60bits hardware ECC
  • For DDR nandflash, support DLL bypass and 1/4 or 1/8 clock adjust, maximum clock rate is 5MHz
  • For async/toggle nandflash, support configurable interface timing , maximum data rate is 16bit/cycle
  • Embedded AHB master interface to do data transfer by DMA method
  • Also support data transfer by AHB slave interface together with external DMAC

• eMMC Interface
  • Compatible with standard iNAND interface
  • Support MMC4.41 protocol
  • Provide eMMC boot sequence to receive boot data from external eMMC device
  • Support FIFO over-run and under-run prevention by stopping card clock automatically
  • Support CRC generation and error detection
  • Embedded clock frequency division control to provide programmable baud rate
  • Support block size from 1 to 65535Bytes
  • 8bits data bus width

• SD/MMC Interface
  • Compatible with SD2.0, MMC 41
  • Support FIFO over-run and under-run prevention by stopping card clock automatically
  • Support CRC generation and error detection
  • Embedded clock frequency division control to provide programmable baud rate
  • Support block size from 1 to 65535Bytes
  • Data bus width is 4bits

• System Component

• CRU (clock & reset unit)
  • Support clock gating control for individual components inside RK3126C
  • One oscillator with 24MHz clock input and 4 embedded PLLs
  • Support global soft-reset control for whole SOC, also individual soft-reset for every components

• PMU(power management unit)
  • Multiple configurable work modes to save power by different frequency or automatically clock gating control or power domain on/off control
  • Lots of wakeup sources in different mode
  • 2 separate voltage domains
  • 3 separate power domains, which can be power up/down by software based on different application scenes

• Timer
  • 6 general Timers and 2 secure timers in SoC with interrupt-based operation
  • Provide two operation modes: free-running and user-defined count
  • Support timer work state checkable
• Fixed 24MHz clock input
• PWM
  • Four on-chip PWMs with interrupt-based operation
  • Programmable pre-scaled operation to bus clock and then further scaled
  • Embedded 32-bit timer/counter facility
  • Support capture mode
  • Support continuous mode or one-shot mode
  • Provides reference mode and output various duty-cycle waveform

• WatchDog
  • 32 bits watchdog counter width
  • Counter clock is from APB bus clock
  • Counter counts down from a preset value to 0 to indicate the occurrence of a timeout
  • WDT can perform two types of operations when timeout occurs:
    • Generate a system reset
    • First generate an interrupt and if this is not cleared by the service routine by the time a second timeout occurs then generate a system reset
  • Programmable reset pulse length
  • Totally 16 defined-ranges of main timeout period

• Bus Architecture
  • 128bit/64-bit/32-bit multi-layer AXI/AHB/APB composite bus architecture
  • 5 embedded AXI interconnect
    • CPU interconnect with four 64-bits AXI masters, one 64-bits AXI slaves, one 32-bits AHB master and lots of 32-bits AHB/APB slaves
    • PERI interconnect with two 64-bits AXI masters, one 64-bits AXI slave, five 32- bits AHB masters and lots of 32-bits AHB/APB slaves
    • Display interconnect with three 128-bits AXI master, four 64-bits AXI masters and one 32-bits AHB slave
    • GPU interconnect with one 128-bits AXI master with point-to-point AXI-lite architecture and 32-bits APB slave
    • VCODEC interconnect also with two 64-bits AXI master and two 32-bits AHB slave, they are point-to-point AXI-lite architecture
  • Flexible different QoS solution to improve the utility of bus bandwidth

• Interrupt Controller
  • Support 3 PPI interrupt source and 74 SPI interrupt sources input from different components inside RK3126C
  • Support 16 software-triggered interrupts
  • Input interrupt level is fixed , only high-level sensitive
  • Two interrupt outputs (nFIQ and nIRQ) separately for each Cortex-A7, both are low-level sensitive
  • Support different interrupt priority for each interrupt source, and they are always software-programmable

• DMAC
  • Micro-code programming based DMA
  • The specific instruction set provides flexibility for programming DMA transfers
  • Linked list DMA function is supported to complete scatter-gather transfer
  • Support internal instruction cache
  • Embedded DMA manager thread
  • Support data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory
  • Signals the occurrence of various DMA events using the interrupt output signals
  • Mapping relationship between each channel and different interrupt outputs is software-programmable

• One embedded DMA controller PERI_DMAC for peripheral system
• PERI_DMAC features:
  • 8 channels totally
  • 16 hardware request from peripherals
  • 2 interrupt output

• Security system
  • Support trustzone technology for the following components
    • Cortex-A7, support security and non-security mode, switch by software
    • 512bit eFuse, only accessed by Cortex-A7 in security mode
    • Internal memory , part of space is addressed only in security mode, detailed size is software-programmable together with TZMA(trustzone memory adapter) and TZPC(trustzone protection controller)

• Video CODEC

• Shared internal memory and bus interface for video decoder and encoder
• Embedded memory management unit(MMU)
• Video Decoder
  • Real-time video decoder of MPEG-1, MPEG-2, MPEG-4,H.263, H.264,VC-1, VP8, MVC
  • MMU Embedded
  • Supports frame timeout interrupt , frame finish interrupt and bit stream error interrupt
  • Error detection and concealment support for all video formats
  • Output data format is YUV420 semi-planar, and YUV400(monochrome) is also supported for 264
  • 264 up to HP level 4.2 : 1080p@30fps
  • MPEG-4 up to ASP level 5 : 1080p@30fps
  • MPEG-2 up to MP : 1080p@30fps
  • MPEG-1 up to MP : 1080p@30fps

n     H.263                               : 576p@60fps

• VC-1 up to AP level 3 : 1080p@30fps

n     VP8                                  : 1080p@30fps

n     MVC                                 : 1080p@30fps

• For 264, image cropping not supported
• For MPEG-4,GMC(global motion compensation)not supported
• For VC-1, up-scaling and range mapping are supported in image post-processor
• For MPEG-4 SP/H.263/Sorenson spark, using a modified H.264 in-loop filter to implement deblocking filter in post-processor unit
• Video Encoder
  • Support video encoder for H.264 UP to HP@level4.1, MVC and VP8
  • Only support I and P slices, not B slices
  • Support error resilience based on constrained intra prediction and slices
  • Input data format:
    • YCbCr 4:2:0 planar
    • YCbCr 4:2:0 semi-planar
    • YCbYCr 4:2:2
    • CbYCrY 4:2:2 interleaved
    • RGB444 and BGR444
    • RGB555 and BGR555
    • RGB565 and BGR565
    • RGB888 and BRG888

u    RGB101010 and BRG101010

• Image size is from 96×96 to 1920×1088(Full HD)
• Maximum frame rate is up to 30fps@1280*720
• Bit rate supported is from 10Kbps to 20Mbps
• JPEG CODEC

• JPEG decoder

n     Input JPEG file : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4 sampling formats

n     Output raw image : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4 semi-planar

• Decoder size is from 48×48 to 8176×8176(66.8Mpixels)
• Support JPEG ROI(region of image) decode
• Maximum data rate is up to 76million pixels per second
• Embedded memory management unit(MMU)
• JPEG encoder
  • Input raw image :
    • YCbCr 4:2:0 planar
    • YCbCr 4:2:0 semi-planar
    • YCbYCr 4:2:2
    • CbYCrY 4:2:2 interleaved
    • RGB444 and BGR444
    • RGB555 and BGR555
    • RGB565 and BGR565
    • RGB888 and BRG888

u    RGB101010 and BRG101010

• Output JPEG file : JFIF file format 1.02 or Non-progressive JPEG
• Encoder image size up to 8192×8192(64million pixels) from 96×32
• Maximum data rate up to 90million pixels per second
• Embedded memory management unit(MMU)
• Image Enhancement (IEP module)

• Image format support
  • Input data: YUV420/YUV422
  • Output data: YUV420/YUV422
  • YUV swap
  • UV SP/P
  • YUV up/down sampling
  • Max source image resolution: 1920×1080
• YUV enhancement
  • Hue, Saturation, Brightness, Contrast adjustment
• De-interlace
  • Source width up to 1920
  • Configured high frequency de-interlace
  • I2O1B/I2O1T mode
• Interface
  • 32bit AHB bus slave
  • 64bit AXI bus master
  • Combined interrupt output

• Graphics Engine
• 3D Graphics Engine :
  • High performance OpenGL ES1.1 and 2.0, OpenVG1.1
  • Embedded 4shader cores with shared hierarchical tiler
  • Separate vertex(geometry) and fragment(pixel) processing for maximum parallel throughput
  • Provide MMU and L2 Cache with 32KB size
  • Triangle rate : 30M triangles/s
  • Pixel rate: 300 pixels/s @ 150MHz
• 2D Graphics Engine(RGA module) :
• Pixel rate: 300M pixel/s without scale, 150M pixel/s with bilinear scale, 5M pixel/s with bicubic scale.
• Bit Blit with Strength Blit, Simple Blit and Filter Blit
• Color fill with gradient fill, and pattern fill
• Line drawing with anti-aliasing and specified width
• High-performance stretch and shrink
• Monochrome expansion for text rendering
• ROP2, ROP3, ROP4 full alpha blending and transparency
• Alpha blending modes including Java 2 Porter-Duff compositing blending rules , chroma key, and pattern mask
• 8K x 8K raster 2D coordinate system
• Arbitrary degrees rotation with anti-aliasing on every 2D primitive
• Programmable bicubic filter to support image scaling
• Blending, scaling and rotation are supported in one pass for stretch blit
• Source formats :

u    ABGR8888, XBGR888, ARGB8888, XRGB888

u    RGB888, RGB565

u    RGBA5551, RGBA4444

• YUV420 planar, YUV420 semi-planar
• YUV422 planar, YUV422 semi-planar
• BPP8, BPP4, BPP2, BPP1

• Destination formats :

u    ABGR8888, XBGR888, ARGB8888, XRGB888

u    RGB888, RGB565

u    RGBA5551, RGBA4444

• YUV420 planar, YUV420 semi-planar only in filter and pre-scale mode
• YUV422 planar, YUV422 semi-planar only in filter and pre-scale mode
• Video IN/OUT

• Camera Interface
  • Support up to 5M pixels
  • 8bits CCIR656(PAL/NTSC) interface
  • 8bits parallel interface
  • YUV422 data input format with adjustable YUV sequence
  • YUV422,YUV420 output format with separately Y and UV space
  • Support picture in picture (PIP)
  • Support image crop with arbitrary windows
• Display Interface
  • Support LCD or TFT interfaces up to 1920×1080
  • Parallel RGB LCD Interface :

RGB888 (24bits), RGB666 (18bits) , RGB565 (15bits)

• Serial RGB LCD Interface: 2×12-bit, 3×8-bit(RGB delta support), 3×8-bit + dummy
• 4 display layers :
  • One background layer with programmable 24bits color
  • One video layer (win0)
    • RGB888, ARGB888, RGB565, YCbCr422, YCbCr420, YCbCr444
    • maximum resolution is 1920×1080,support virtual display
    • 1/8 to 8 scaling up/down engine with arbitrary non-integer ratio
    • 256 level alpha blending(pre-multiplied alpha support)
    • Support transparency color key
    • De-flicker support for interlace output
    • Direct path support
    • YCbCr2RGB(rec601-mpeg/rec601-jpeg/rec709)
    • RGB2YCbCr(BT601/BT709)
  • One video layer (win1)

l     RGB888, ARGB888, RGB565

• Support virtual display
• 256 level alpha blending (pre-multiplied alpha support)
• Support transparency color key
• Direct path support
• RGB2YCbCr(BT601/BT709)
• Hardware cursor(win3)
  • 8BPP (ARGB888 LUT)
  • Support two size: 32×32 and 64×64
  • 256 level alpha blending
  • Support HWC over panel at right and below side
• Win0 and Win1 layer overlay exchangeable
• 3 x 256 x 8 bits display LUTs
• Support replication(16bits to 24bits) and dithering(24bits to 16bits/ 18bits) operation
• Blank and blank display
• Scaler
  • Output for LVDS/RGB (max up to 1024×768)

• MIPI Interface
• Embedded 1 MIPI DPHY for TX
• Support 4 data lane
• Support 1080p @ 60fps output
• LVDS
• 135MHz clock support
• 28:4 data sub channel compression at data rates up to 945 Mbps per channel
• Support VGA,SVGA,XGA and single pixel SXGA
• PLL requires no external components
• Comply with the Standard TIA/EIA-644-A LVDS standard
• Support alternative LVDS output or LVTTL output
• Audio Interface

• I2S/PCM with 2ch
  • Up to 2 channels (2xTX, 2xRX)
  • Audio resolution from 16bits to 32bits
  • Sample rate up to 192KHz
  • Provides master and slave work mode, software configurable
  • Support 3 I2S formats (normal , left-justified , right-justified)
  • Support 4 PCM formats(early , late1 , late2 , late3)
  • I2S and PCM cannot be used at the same time

• Audio Codec
  • 18 to 24 bit High Order Sigma-Delta modulation for DAC for >93 dB SNR configurable
  • 16 to 18 bit High Order Sigma-Delta modulation for ADC for >90 dB SNR configurable
  • Digital interpolation and decimation filter integrated
  • Line-in, Microphone in and Speaker out Interface
  • On-Chip Analog Post Filter and digital filters
  • Single–ended or differential Input and Output
  • Sampling Rate of 8kHz/12kHz/16kHz/ 24kHz/32kHz /48kHz/44.1K/96KHz
  • Support 16ohm to 32ohm Head Phone and Speaker Phone Output
  • Mono, Stereo channel supported
  • Optional Fractional PLL available that support 6Mhz to 20Mhz clock input to any clock output that meets 8kHz/12kHz/16kHz/ 24kHz/32kHz /48kHz/44.1K/96KHz and 128 time oversampling

• Connectivity

• SDIO interface
  • Compatible with SDIO 3.0 protocol
  • 4bits data bus widths

• SPI Controller
  • 1 on-chip SPI controller
  • Support serial-master and serial-slave mode, software-configurable
  • DMA-based or interrupt-based operation
  • Embedded two 32x16bits FIFO for TX and RX operation respectively
  • Support 2 chip-selects output in serial-master mode

• UART Controller
  • 2 on-chip uart controller inside RK3126C
  • DMA-based or interrupt-based operation
  • UART1/UART2 Embedded two 32Bytes FIFO for TX and RX operation respectively
  • Support 5bit,6bit,7bit,8bit serial data transmit or receive
  • Standard asynchronous communication bits such as start,stop and parity
  • Support different input clock for uart operation to get up to 4Mbps or other special baud rate
  • Support non-integer clock divides for baud clock generation
  • Support auto flow control mode

• I2C controller
  • 3 on-chip I2C controller in RK3126C
  • Multi-master I2C operation
  • Support 7bits and 10bits address mode
  • Software programmable clock frequency and transfer rate up to 400Kbit/s in the fast mode
  • Serial 8bits oriented and bidirectional data transfers can be made at up to 100Kbit/s in the standard mode

 

• GPIO
  • 4 groups of GPIO (GPIO0~GPIO3) , 32 GPIOs per group in GPIO0~GPIO3, totally have 128 GPIOs
  • All of GPIOs can be used to generate interrupt to Cortex-A7
  • All of pull-up GPIOs are software-programmable for pull-up resistor or not
  • All of pull-down GPIOs are software-programmable for pull-down resistor or not
  • All of GPIOs are always in input direction in default after power-on-reset

• USB 0
  • Embedded 1 USB Host2.0 interfaces
  • Compatible with USB Host2.0 specification
  • Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
  • Provides 16 host mode channels
  • Support periodic out channel in host mode

• USB 0
  • Compatible with USB 0 specification
  • Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
  • Support up to 9 device mode endpoints in addition to control endpoint 0
  • Support up to 6 device mode IN endpoints including control endpoint 0
  • Endpoints 1/3/5/7 can be used only as data IN endpoint
  • Endpoints 2/4/6 can be used only as data OUT endpoint
  • Endpoints 8/9 can be used as data OUT and IN endpoint
  • Provides 9 host mode channels

• Others

• SAR-ADC(Successive Approximation Register)
  • 3-channel single-ended 10-bit SAR analog-to-digital converter
  • Sample rate Fs is 200KHz
  • SAR-ADC clock must be large than 11*Fs, recommend is 11*Fs
  • DNL is less than ±1 LSB , INL is less than ±0 LSB
  • Power supply is 3.3V (±10%) for analog interface, power dissipation is less than 900uW

• eFuse
  • Two 512bit high-density electrical Fuse is integrated, and one of them is secure access only
  • Support standby mode
  • Programming condition : VP must be 5V(±10%)

Provide inactive mode, VP must be 0V or Floating in this mode.