瑞芯微RK3128芯片简介

瑞芯微RK3128芯片简介，RK3128是一款高性价比的通用型SoC，非常适合大规模部署的项目。RK3128官方支持安卓系统，有第三方的Linux系统，目前主要用于数字标牌、平板电脑等产品。

RK3128 is a high performance Quad-core application processor for smart TV-Box. Especially it is a high-integration and cost efficient SOC for 1080P H.265 TV-Box.

Quad-core Cortex-A7 is integrates with separately Neon and FPU coprocessor. Mali400 MP2 GPU is embedded to support smoothly high-resolution (1080p) display and mainstream game.

Lots of high-performance interface to get very flexible solution, such as multi-pipe display with HDMI1.4, TV Encoder. Crypto hardware is integrated for support security BOOT. 32bits DDR3/LPDDR2 provides high memory bandwidths for high-performance.

HEVC hardware is integrated for support 1080P H.265 video.

1.1  Features

1.1.2  Microprocessor

• Quad-core ARM Cortex-A7MP Core processor, a high-performance, low-power and cached application processor
• Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
• Separately Integrated Neon and FPU per CPU
• 32KB/32KB L1 I-Cache/D-Cache per
• Unified 256KB L2

 

1.1.3  Memory Organization

• Internal on-chip memory
  • BootRom
  • Internal SRAM
• External off-chip memory①
  • DDR3/DDR3L/LPDDR2
  • Async/Toggle/SyncNand Flash(include LBA Nand)

 

1.1.4  Internal Memory

• Internal BootRom
  • Support system boot from the following device :
    • 8bits Async Nand Flash
    • 8bits toggle Nand Flash
    • SPI interface
    • eMMC interface
    • SDMMC interface
  • Support system code download by the following interface:
    • USB OTG interface
  • Internal SRAM
    • Size : 8KB

1.1.5  External Memory or Storage device

• Dynamic Memory Interface (DDR3/DDR3L/LPDDR2)
  • Compatible with JEDEC standard DDR3-1066/DDR3L-1066/LPDDR2-800 SDRAM
  • Supports 32 Bits data width, 2 ranks (chip selects), totally 2GB (max) address
  • 7 host ports with 64bits/128bits AXI bus interface for system access, AXI bus clock

is asynchronous with DDR clock

• Programmable timing parameters to support DDR3/DDR3L/LPDDR2 SDRAM from various vendor
• Advanced command reordering and scheduling to maximize bus utilization
• Low power modes, such as power-down and self-refresh for DDR3/LPDDR2 SDRAM; clock stop and deep power-down for LPDDR2 SDRAM
• Compensation for board delays and variable latencies through programmable pipelines
• Programmable output and ODT impedance with dynamic PVT compensation
• Nand Flash Interface
  • Support 8bits async/toggle/syncnandflash, up to 4 banks
  • Support LBA nandflash
  • 16bits, 24bits, 40bits, 60bits hardware ECC
  • For DDR nandflash, support DLL bypass and 1/4 or 1/8 clock adjust
  • For async/togglenandflash, support configurable interface timing, maximum data rate is 16bit/cycle
  • Embedded AHB master interface to do data transfer by DMA method
  • Also support data transfer by AHB slave interface together with external DMAC

• eMMC Interface
  • Compatible with standard iNAND interface
  • Support MMC4.5 protocol
  • Provide eMMC boot sequence to receive boot data from external eMMC device
  • Support FIFO   over-run   and   under-run   prevention   by   stopping  card   clock automatically
  • Support CRC generation and error detection
  • Embedded clock frequency division control to provide programmable baud rate
  • Support block size from 1 to 65535Bytes
  • 8bits data bus width

• SD/MMC Interface
  • Compatible with SD2.0, MMC ver 5
  • Support FIFO   over-run   and   under-run   prevention   by   stopping  card   clock automatically
  • Support CRC generation and error detection
  • Embedded clock frequency division control to provide programmable baud rate
  • Support block size from 1 to 65535Bytes
  • Data bus width is 4bits

 

1.1.6  System Component

• CRU (clock & reset unit)
  • Support clock gating control for individual components inside RK3128
  • One oscillator with 24MHz clock input and 4 embedded PLLs
  • Support global soft-reset control for whole SOC, also individual soft-reset for every components
• PMU(power management unit)
  • Multiple configurable work modes to save power by different frequency or automatically clock gating control or power domain on/off control
  • Lots of wakeup sources in different mode
  • 2 separate voltage domains
  • 3 separate power domains, which can be power up/down by software based on different application scenes
• Timer
• 6 on-chip 64bits Timers in SoC with interrupt-based operation
• Provide two operation modes: free-running and user-defined count
• Support timer work state checkable
• Fixed 24MHz clock input
• PWM
  • Four on-chip PWMs with interrupt-based operation
  • Programmable pre-scaled operation to bus clock and then further scaled
  • Embedded 32-bit timer/counter facility
  • Support capture mode
  • Support continuous mode or one-shot mode
  • Provides reference mode and output various duty-cycle waveform

• WatchDog
  • 32 bits watchdog counter width
  • Counter clock is from apb bus clock
  • Counter counts down from a preset value to 0 to indicate the occurrence of a timeout
  • WDT can perform two types of operations when timeout occurs:
    • Generate a system reset
    • First generate an interrupt and if this is not cleared by the service routine by the time a second timeout occurs then generate a system reset
  • Programmable reset pulse length
  • Totally 16 defined-ranges of main timeout period

• Bus Architecture
  • 128bit/64-bit/32-bit multi-layer AXI/AHB/APB composite bus architecture
  • 5 embedded AXI interconnect
    • CPU interconnect with four 64-bits AXI masters, one 64-bits AXI slaves, one 32- bits AHB master and lots of 32-bits AHB/APB slaves
    • PERI interconnect with two 64-bits AXI masters, one 64-bits AXI slave, five 32- bits AHB masters and lots of 32-bits AHB/APB slaves
    • Display interconnect with three 128-bits AXI master, four 64-bits AXI masters and one 32-bits AHB slave
    • GPU interconnect with one 128-bits AXI master with point-to-point AXI-lite architecture and 32-bits APB slave
    • VCODEC interconnect also with two 64-bits AXI master and two 32-bits AHB slave, they are point-to-point AXI-lite architecture
  • Flexible different QoS solution to improve the utility of bus bandwidth

• Interrupt Controller
  • Support 3 PPI interrupt source and 74 SPI interrupt sources input from different components inside RK3128
  • Support 16 softwre-triggered interrupts
  • Input interrupt level is fixed , only high-level sensitive
  • Two interrupt outputs (nFIQ and nIRQ)separatelyfor each Cortex-A7, both are low- level sensitive
  • Support different interrupt priority for each interrupt source, and they are always software-programmable

• DMAC
  • Micro-code programming based DMA
  • The specific instruction set provides flexibility for programming DMA transfers
  • Linked list DMA function is supported to complete scatter-gather transfer
  • Support internal instruction cache
  • Embedded DMA manager thread
  • Support data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory

• Signals the occurrence of various DMA events using the interrupt output signals
• Mapping relationship between each channel and different interrupt outputs is software-programmable
• One embedded DMA controller PERI_DMAC for peripheral system
• PERI_DMAC features:
  • 8 channels totally
  • 16 hardware request from peripherals
  • 2 interrupt output
  • Not support trustzone technology

• Security system
  • Embedded encryption and decryption engine
    • Support AES 128/192/256 bits key mode, ECB/CBC/CTR chain mode, Slave/FIFO mode
    • Support DES/3DES (ECB and CBC chain mode) , 3DES (EDE/ EEE key mode), Slave/FIFO mode
    • Support SHA1/SHA256/MD5  (with  hardware padding) HASH function, FIFO mode only
    • Support 160 bit Pseudo Random Number Generator (PRNG)
    • Support PKA 512/1024/2048 bit Exp Modulator

1.1.7  Video CODEC

• Shared internal memory and bus interface for video decoder and encoder②
• Embedded memory management unit(MMU)
• Video Decoder
  • Real-time video decoder of MPEG-1, MPEG-2, MPEG-4,H.263, H.264, 265,VC-1, VP8, MVC
  • MMU Embedded
  • Supports frame timeout interrupt , frame finish interrupt and bitstream error interrupt
  • Error detection and concealment support for all video formats
  • Output data format is YUV420 semi-planar, and YUV400(monochrome) is also supported for 264
  • 265 up to MP Level 4.1 High Tier : 1080P@60fps
  • 264 up to HP level 4.2 : 1080p@60fps
  • MPEG-4 up to ASP level 5 : 1080p@60fps
  • MPEG-2 up to MP : 1080p@60fps
  • MPEG-1 up to MP : 1080p@60fps
  • H.263  : 576p@60fps

• VC-1 up to AP level 3 : 1080p@30fps
• VP8: 1080p@60fps
• MVC: 1080p@60fps
• For 264, image cropping not supported
• For MPEG-4,GMC(global motion compensation)not supported
• For VC-1, upscaling and range mapping are supported in image post-processor
• For MPEG-4 SP/H.263, using a modified 264 in-loop filter to implement deblocking filter in post-processor unit
• Video Encoder
  • Support video encoder for H.264 UP to HP@level4.1, MVC and VP8
  • Only support I and P slices, not B slices
  • Support error resilience based on constrained intra prediction and slices
  • Input data format:
    • YCbCr 4:2:0 planar
    • YCbCr 4:2:0 semi-planar
    • YCbYCr 4:2:2

• CbYCrY 4:2:2 interleaved
• RGB444 and BGR444
• RGB555 and BGR555
• RGB565 and BGR565
• RGB888 and BRG888
• RGB101010 and BRG101010

• Image size is from 96×96 to 1920×1088(Full HD)
• Maximum frame rate is up to 1920×1080 @ 30FPS③

1.1.8  JPEG CODEC

• JPEG decoder
  • Input JPEG file : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4 sampling formats
  • Output raw image : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4 semi-planar
• Decoder size is from 48×48 to 8176×8176(66.8Mpixels)
• Support JPEG ROI(region of image) decode
• Maximum data rate④ is up to 76million pixels per second
• Embedded memory management unit(MMU)
• JPEG encoder
  • Input raw image :
    • YCbCr 4:2:0 planar
    • YCbCr 4:2:0 semi-planar
    • YCbYCr 4:2:2
    • CbYCrY 4:2:2 interleaved
    • RGB444 and BGR444
    • RGB555 and BGR555
    • RGB565 and BGR565
    • RGB888 and BRG888
    • RGB101010 and BRG101010
• Output JPEG file : JFIF file format 1.02 or Non-progressive JPEG
• Encoder image size up to 8192×8192(64million pixels) from 96×32
• Maximum data rate④ up to 90million pixels per second
• Embedded memory management unit(MMU)

1.1.9  Image Enhancement (IEP module)

• Image format support
  • Input data: XRGB/RGB565/YUV420/YUV422
  • Output data: ARGB/RGB565/YUV420/YUV422
  • ARGB/XRGB/RGB565/YUV swap
  • UV SP/P
  • BT601_l/BT601_f/BT709_l/BT709_f color space conversion
  • RGB dither up/down
  • YUV up/down sampling
  • Max source image resolution: 8192×8192
  • Max scaled image resolution: 4096×4096
• YUV enhancement
  • Hue, Saturation, Brightness, Contrast adjustment
• RGB enhancement & denoise
  • Contrast enhancement
  • Color enhancement
  • Gamma adjustment
• High quality scale
  • Averaging filter down-scaling
  • Bi-cubic up-scaling

• Arbitrary non-integer horizontal & vertical scaling ratio range from 1/16 to 16

• De-interlace
  • 3×5 Y motion detection matrix
  • Source width up to 1920
  • Configured high frequency de-interlace
  • I4O2 (Input 4 field, output 2 frame) /I4O1B/I4O1T/I2O1B/I2O1T mode
• Interface
  • Configured direct path to LCDC if source width no more than 1920
  • 32bit AHB bus slave
  • 64bit AXI bus master
  • Combined interrupt output

1.1.10  Graphics Engine

• 3D Graphics Engine :
  • High performance OpenGL ES1.1 and 2.0, OpenVG1.1
  • Embedded 4 shader cores with shared hierarchical tiler
  • Separate vertex(geometry) and fragment(pixel) processing for maximum parallel throughput
  • Provide MMU and L2 Cache with 32KB size
• 2D Graphics Engine(RGA module) :
  • Bit Blit with Strength Blit, Simple Blit and Filter Blit
  • Color fill with gradient fill, and pattern fill
  • Line drawing with anti-aliasing and specified width
  • High-performance stretch and shrink
  • Monochrome expansion for text rendering
  • ROP2, ROP3, ROP4 full alpha blending and transparency
  • Alpha blending modes including Java 2 Porter-Duff compositing blending rules , chroma key, and pattern mask
  • 8K x 8K raster 2D coordinate system
  • Arbitrary degrees rotation with anti-aliasing on every 2D primitive
  • Programmable bicubic filter to support image scaling
  • Blending, scaling and rotation are supported in one pass for stretch blit
  • Source formats : ABGR8888, XBGR888, ARGB8888, XRGB888,RGB888, RGB565,RGBA5551, RGBA4444

• YUV420 planar, YUV420 semi-planar
• YUV422 planar, YUV422 semi-planar
• BPP8, BPP4, BPP2, BPP1

• Destination formats : ABGR8888, XBGR888, ARGB8888, XRGB888, RGB888, RGB565,RGBA5551, RGBA4444

• YUV420 planar, YUV420 semi-planar only in filter and pre-scale mode
• YUV422 planar, YUV422 semi-planar only in filter and pre-scale mode

 

1.1.11  Video IN/OUT

• Camera Interface
  • Support up to 5M pixels
  • 8bits CCIR656(PAL/NTSC) interface
  • 8bits raw data interface
  • YUV422 data input format with adjustable YUV sequence
  • YUV422,YUV420 output format with separately Y and UV space
  • Support image crop with arbitrary windows

• Display Interface
  • Support HDMI 1.4 output up to 1080P@60Hz
  • TV Interface: ITU-R 656(8-bit, 480i/576i/1080i),TV encoder 10bit out for DAC, RGB888+1080i for HDMI, Parallel RGB HDMI interface:24-bit(RGB888 YCbCr444)
  • Max output resolution 1920×1080 for HDMI, 480i/576i for CVBS
  • 4 display layers :
    • One background layer with programmable 24bits color
    • One video layer (win0)
      • RGB888, ARGB888, RGB565, YCbCr422, YCbCr420, YCbCr444
      • maximum resolution is 1920×1080,support virtual display
      • 1/8 to 8 scaling up/down engine with arbitrary non-integer ratio
      • 256 level alpha blending(pre-multiplied alpha support)
      • Support transparency color key
      • De-flicker support for interlace output
      • Direct path support
      • YCbCr2RGB(rec601-mpeg/rec601-jpeg/rec709)
      • RGB2YCbCr(BT601/BT709)
    • One video layer (win1)

l     RGB888, ARGB888, RGB565

• Support virtual display
• 256 level alpha blending (pre-multiplied alpha support)
• Support transparency color key
• Direct path support
• RGB2YCbCr(BT601/BT709)

• Hardware cursor(win3)
  • 8BPP (ARGB888 LUT)
  • Support two size: 32×32 and 64×64
  • 256 level alpha blending
  • Support hwc over panel at right and below side
• Win0 and Win1 layer overlay exchangeable
• 3 x 256 x 8 bits display LUTs
• Support replication (16bits to 24bits) and dithering(24bits to 16bits/ 18bits) operation
• Blank and blank display
• Scaler
  • Output for RGB/LVDS (max up to 1024×768), not support interlace

1.1.12  LVDS

• Up to 135MHz clock support
• 28:4 data sub channel compression at data rates up to 945 Mbps per channel
• Support VGA, SVGA,XGA and single pixel SXGA
• PLL requires no external components
• Comply with the Standard TIA/EIA-644-A LVDS standard
• Support alternative LVDS output or LVTTL output

1.1.13  MIPI DPHY

• Embedded 1 MIPI DPHY for TX
• Support 4 data lane
• Support 1080p @ 60fps output

1.1.14  HDMI

• HDMI version 1.4a, HDCP revision 1.4 and DVI version 1.0 compliant transmitter
• Supports DTV from 480i to 1080i/p HD resolution
• Supports 3D function defined in HDMI 1.4 spec
• Supports data rate from 25MHz, 1.65bps up to 3.4Gbps over a Single channel HDMI
• TMDS Tx Drivers with programmable output swing, resister values and pre-emphasis
• Digital video interface supports a pixel size of 24, 30, 36, 48bits color depth in RGB
• S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission (32- 192kHz Fs) using IEC60958 and IEC 61937
• Multiphase 4MHz fixed bandwidth PLL with low jitter
• HDCP encryption and decryption engine contains all the necessary logic to encrypt the incoming audio and video data
• Support HDMI LipSync if needed as addon feature
• Lower power operation with optimal power management feature
• The EDID and CEC function are also supported by HDMI Transmitter Controller
• Optional Monitor Detection supported through Hot Plug

1.1.15  Audio Interface

• I2S/PCM with 8ch
  • Up to 8 channels (8xTX, 2xRX)
  • Audio resolution from 16bits to 32bits
  • Sample rate up to 192KHz
  • Provides master and slave work mode, software configurable
  • Support 3 I2S formats (normal, left-justified, right-justified)
  • Support 4 PCM formats(early, late1, late2, late3)
  • I2S and PCM mode cannot be used at the same time

• I2S/PCM with 2ch
  • Up to 2 channels (2xTX, 2xRX)
  • Audio resolution from 16bits to 32bits
  • Sample rate up to 192KHz
  • Provides master and slave work mode, software configurable
  • Support 3 I2S formats (normal , left-justified , right-justified)
  • Support 4 PCM formats(early , late1 , late2 , late3)
  • I2S and PCM cannot be used at the same time

• SPDIF
  • Support two 16-bit audio data store together in one 32-bit wide location
  • Support biphase format stereo audio data output
  • Support 16 to 31 bit audio data left or right justified in 32-bit wide sample data buffer
  • Support 16, 20, 24 bits audio data transfer in linear PCM mode
  • Support non-linear PCM transfer
• Audio Codec
  • Digital interpolation and decimation filter integrated
  • Line-in, Microphone in and Speaker out Interface
  • On-Chip Analog Post Filter and digital filters
  • Single–ended or differential Input and Output
  • Sampling Rate of 8kHz/12kHz/16kHz/ 24kHz/32kHz /48kHz/44.1K/96KHz
  • Support 16ohm to 32ohm Head Phone and Speaker Phone Output
  • Mono, Stereo channel supported
  • Optional Fractional PLL available that support 6Mhz to 20Mhz clock input to any clock output that meets 8kHz/12kHz/16kHz/ 24kHz/32kHz /48kHz/44.1K/96KHz and 128 time oversampling

1.1.16  Connectivity

• SDIO interface
  • Compatible with SDIO 3.0 protocol
  • 4bits data bus widths
• High-speed ADC stream interface
• Support single-channel 8bits/10bits interface
• DMA-based and interrupt-based operation
• Support 8bits TS stream interface
• TS interface
  • Supports one TS input
  • Supports 4 TS Input Mode: sync/valid mode in the case of serial TS input; nosync/valid mode, sync/valid, sync/burst mode in the case of parallel TS
  • Supports 2 TS sources: demodulators and local
  • Supports 1   Built-in  PTIs(Programmable   Transport  Interface)   to   process   TS simultaneously, and Each PTI supports:
    • 64 PID
    • TS descrambling with 16 sets of Control Word under CSA v2.0 standard, up to 104Mbps
    • 16 PES/ES filters with PTS/DTS extraction and ES start code
    • 4 PCR extraction channels
    • 64 Section filters with CRC check, and three interrupt mode: stop per unit, full- stop, recycle mode with version number check
    • PID done and error interrupts for each channel
    • PCR/DTS/PTS extraction interrupt for each channel
  • 1 built-in multi-channel DMA

• Smart Card
  • support card activation and deactivation
  • support cold/warm reset
  • support Answer to Reset (ATR) response reception
  • support T0 for asynchronous half-duplex character transmission
  • support T1 for asynchronous half-duplex block transmission
  • support automatic operating voltage class selection
  • support adjustable clock rate and bit (baud) rate
  • support configurable automatic byte repetition

• GMAC 10/100/1000M Ethernet Controller
  • Supports 10/100/1000-Mbps data transfer rates with the RGMII interfaces
  • Supports 10/100-Mbps data transfer rates with the RMII interfaces
  • Supports both full-duplex and half-duplex operation
    • Supports CSMA/CD Protocol for half-duplex operation
    • Supports packet bursting and frame extension in 1000 Mbps half-duplex operation
    • Supports IEEE 802.3x flow control for full-duplex operation
    • Optional forwarding of received pause control frames to the user application in full-duplex operation
    • Back-pressure support for half-duplex operation
    • Automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-duplex operation
  • Preamble and start-of-frame data (SFD) insertion in Transmit, and deletion in Receive paths
  • Automatic CRC and pad generation controllable on a per-frame basis
  • Options for Automatic Pad/CRC Stripping on receive frames
  • Programmable InterFrameGap (40-96 bit times in steps of 8)
  • Supports a variety of flexible address filtering modes
  • Separate 32-bit status returned for transmission and reception packets
  • Supports IEEE 802.1Q VLAN tag detection for reception frames
  • Support detection of LAN wake-up frames and AMD Magic Packet frames
  • Support checksum off-load for received IPv4 and TCP packets encapsulated by the Ethernet frame
  • Support checking IPv4 header checksum and TCP, UDP, or ICMP checksum

encapsulated in IPv4 or IPv6 datagrams

• Comprehensive status reporting for normal operation and transfers with errors
• Automatic generation of PAUSE frame control or backpressure signal to the GMAC core based on Receive FIFO-fill (threshold configurable) level
• Handles automatic retransmission of Collision frames for transmission
• Discards frames on late collision, excessive collisions, excessive deferral and underrun conditions
• SPI Controller
  • Support serial-master and serial-slave mode, software-configurable
  • DMA-based or interrupt-based operation
  • Embedded two 32x16bits FIFO for TX and RX operation respectively
  • Support 2 chip-selects output in serial-master mode

• UART Controller
  • 3 on-chip uart controller inside RK3128
  • DMA-based or interrupt-based operation
  • UART0 Embeddeds two 64Bytes FIFO for TX and RX operation respectively
  • UART1/UART2 Embedded two 32Bytes FIFO for TX and RX operation respectively
  • Support 5bit,6bit,7bit,8bit serial data transmit or receive
  • Standard asynchronous communication bits such as start,stop and parity
  • Support different input clock for uart operation to get up to 4Mbps or other special baud rate
  • Support non-integer clock divides for baud clock generation
  • Support auto flow control mode

• I2C controller
  • 4 on-chip I2C controller in RK3128
  • Multi-master I2C operation
  • Support 7bits and 10bits address mode
  • Software programmable clock frequency and transfer rate up to 400Kbit/s in the fast mode
  • Serial 8bits oriented and bidirectional data transfers can be made at up to 100Kbit/s in the standard mode

• GPIO
  • 4 groups of GPIO (GPIO0~GPIO3) , 32 GPIOs per group in GPIO0~GPIO3, totally have 128 GPIOs
  • All of GPIOs can be used to generate interrupt to Cortex-A9
  • All of pullup GPIOs are software-programmable for pullup resistor or not
  • All of pulldown GPIOs are software-programmable for pulldown resistor or not
  • All of GPIOs are always in input direction in default after power-on-reset

• USB 0
  • Embedded 1 USB Host 2.0 interfaces
  • Compatible with USB Host2.0 specification
  • Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
  • Provides 16 host mode channels
  • Support periodic out channel in host mode

• USB 0
  • Compatible with USB OTG2.0 specification
  • Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
  • Support up to 9 device mode endpoints in addition to control endpoint 0
  • Support up to 6 device mode IN endpoints including control endpoint 0
  • Endpoints 1/3/5/7 can be used only as data IN endpoint
• Endpoints 2/4/6 can be used only as data OUT endpoint
• Endpoints 8/9 can be used as data OUT and IN endpoint
• Provides 9 host mode channels

1.1.17  Others

• SAR-ADC(Successive Approximation Register)
  • 3-channel single-ended 10-bit SAR analog-to-digital converter
  • Sample rate Fs is 200KHz
  • SAR-ADC clock must be large than 11*Fs, recommend is 11*Fs

• eFuse
  • Two high-density electrical Fuse is integrated: 512bits (64×8)
  • Support standby mode
  • Provide inactive mode, VP must be 0V or Floating in this
• Package Type

BGA316 (body: 14mm x 14mm ; ball size : 0.3mm ; ball pitch : 0.65mm)

Rockchip RK3128 Datasheet