瑞芯微RV1108芯片简介，视频编解码专用SoC

RV1108是一款高性能、低功耗的视频类应用处理器。RV1108嵌入了新一代数字信号处理器（DSP）和ARM Cortex-A7单核处理器，用于系统和应用。特别是它是一款集成度高、性价比高的SoC，可以支持高达1440p的H.264视频编解码器，同时支持多达4个摄像头输入，将不同的摄像机源合并在一起，在一个屏幕上显示。支持串行接口和并行接口，如串行接口和并行接口。适用于各种应用场景，如车载DVR、运动DV、无人机摄像头、人脸识别和安防摄像头等。

1.1 Features

1.1.1 Microprocessor
 Single-core ARM Cortex-A7 Core processor, a high-performance, low-power and cached application processor
 Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
 Separately integrated NEON and FPU
 32KB/32KB L1 I-Cache/D-Cache
 Unified 128KB L2 Cache.
 Trustzone technology support
1.1.2 Video/Image Digital Signal Processor
 32KB I-TCM and 32KB I-cache
 128KB D-TCM
1.1.3 Memory Organization
 Internal on-chip memory
 BootRom
 Internal SRAM
 External off-chip memory①
 DDR3/DDR3L
 Async NAND Flash
1.1.4 Internal Memory
 Internal BootRom
 Size : 10KB
 Support system boot from the following device :
 8bits Async NAND Flash
 SPI interface
 eMMC interface
 SDMMC interface
 Support system code download by the following interface:
 USB OTG interface
 Internal SRAM
 Size : 12KB
1.1.5 External Memory or Storage device
 Dynamic Memory Interface (DDR3/DDR3L)
 Compatible with JEDEC standard DDR3-1600/DDR3L-1600 SDRAM
 Supports 16 Bits data width, 1 ranks (chip selects), totally 512MB (max) address space.
 Programmable timing parameters to support DDR3/DDR3L SDRAM from various vendor
 Advanced command reordering and scheduling to maximize bus utilization
 Low power modes, such as power-down and self-refresh for DDR3 SDRAM; Compensation for board delays and variable latencies through programmable pipelines
 Programmable output and ODT impedance with dynamic PVT compensation
 NAND Flash Interface
 Support 8bits async NAND flash
 16bits hardware ECC
 For async NAND flash, support configurable interface timing,
 maximum data rate is 8bit/cycle
 Embedded AHB master interface to do data transfer by DMA method
 eMMC Interface
 Compatible with standard iNAND interface
 Support MMC4.51 protocol
 Provide eMMC boot sequence to receive boot data from external eMMC device
 Support FIFO over-run and under-run prevention by stopping card clock automatically
 Support CRC generation and error detection
 Embedded clock frequency division control to provide programmable baud rate
 Support block size from 1 to 65535Bytes
 8bits data bus width
 SD/MMC Interface
 Compatible with SD3.0, MMC ver4.51
 Support FIFO over-run and under-run prevention by stopping card clock automatically
 Support CRC generation and error detection
 Support block size from 1 to 65535Bytes
 Data bus width is 4bits
1.1.6 System Component
 CRU (clock & reset unit)
 Support clock gating control for individual components inside RV1108
 One oscillator with 24MHz clock input and 3 embedded PLLs
 Support global soft-reset control for whole SOC, also individual soft-reset for every components
 Timer
 2 on-chip 64bits Timers in SoC with interrupt-based operation
 Provide two operation modes: free-running and user-defined count
 Support timer work state checkable
 Fixed 24MHz clock input
 PWM
 Eight on-chip PWMs with interrupt-based operation
 Programmable pre-scaled operation to bus clock and then further scaled
 Embedded 32-bit timer/counter facility
 Support capture mode
 Support continuous mode or one-shot mode
 Provides reference mode and output various duty-cycle waveform
 WatchDog
 32 bits watchdog counter width
 Counter clock is from APB bus clock
 Counter counts down from a preset value to 0 to indicate the occurrence of a timeout
 WDT can perform two types of operations when timeout occurs:
 Generate a system reset
 First generate an interrupt and if this is not cleared by the service routine by the time a second timeout occurs then generate a system reset
 Programmable reset pulse length
 Totally 16 defined-ranges of main timeout period
 Bus Architecture
 128bit/64-bit/32-bit multi-layer AXI/AHB/APB composite bus architecture
 5 embedded AXI interconnect
 CPU interconnect with one 128-bits AXI masters, one APB slaves
 DSP interconnect with two 128-bits AXI masters, one 128-bits AXI slave, one 32-bits APB master and many 32-bits APB slaves
 PERI interconnect with eight 32-bits AHB masters and lots of 32-bits AHB/APB slaves
 Display interconnect with two 128-bits AXI master, seven 64-bits AXI masters and lots 32-bits AHB/APB slave
 VENC interconnect with two 128-bits AXI masters, and one 32-bits AHB slaves
 VDEC interconnect also with two 64-bits AXI master and two 32-bits AHB slaves
 Flexible different QoS solution to improve the utility of bus bandwidth
 Interrupt Controller
 Support 3 PPI interrupt source and 128 SPI interrupt sources input from different components inside RV1108
 Support 16 software-triggered interrupts
 Input interrupt level is fixed , only high-level sensitive
 Two interrupt outputs (nFIQ and nIRQ)separately for each Cortex-A7, both are low-level sensitive
 Support different interrupt priority for each interrupt source, and they are always software-programmable
 One non-maskable interrupt for DSP
 Four hardware maskable interrupts for DSP
 Four software maskable interrupts
 DMAC
 Micro-code programming based DMA
 The specific instruction set provides flexibility for programming DMA transfers
 Linked list DMA function is supported to complete scatter-gather transfer
 Support internal instruction cache
 Embedded DMA manager thread
 Support data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory
 Signals the occurrence of various DMA events using the interrupt output signals
 Mapping relationship between each channel and different interrupt outputs is software-programmable
 One embedded DMA controller for system
 DMAC features:
 8 channels totally
 16 hardware request from peripherals
 2 interrupt output
 Dual APB slave interface for register configuration, designated as secure and non-secure
 Support trustzone technology and programmable secure state for each DMA channel
 Security system
 Embedded encryption and decryption engine
 Support AES 128/192/256 bits key mode, ECB/CBC/CTR chain mode, Slave/FIFO mode
 Support DES/3DES (ECB and CBC chain mode) , 3DES (EDE/ EEE key mode), Slave/FIFO mode
 Support SHA1/SHA256/MD5 (with hardware padding) HASH function, FIFO mode only
 Support 160 bit Pseudo Random Number Generator (PRNG)
 Support PKA 512/1024/2048 bit Exp Modulator
1.1.7 Camera interface
 ISP
 Generic Sensor Interface with programmable polarity for synchronization signals
 ITU-R BT 601/656 compliant video interface supporting YCbCr or RGB Bayer data
 12 bit camera interface
 12 bit resolution per color component internally
 YCbCr 4:2:2 processing
 Flash light control
 Mechanical shutter support
 Windowing and frame synchronization
 Frame skip support for video (e.g. MPEG-4) encoding
 Macro block line, frame end, capture error, data loss interrupts and sync. (h_start, v_start) interrupts
 Luminance/chrominance and chrominance blue/red swapping for YUV input signals
 Continuous resize support
 Buffer in system memory organized as ring-buffer
 Buffer overflow protection for raw data
 Asynchronous reset input, software reset for the entire IP and separate software resets for all sub-modules
 Interconnect test support
 Semi planar storage format
 Color processing (contrast, saturation, brightness, hue, offset, range)
 Power management by software controlled clock disabling of currently not needed sub-modules
 Read port provided to read back a picture from system memory
 Black level compensation
 Four channel Lens shade correction (Vignetting)
 Auto focus measurement
 White balancing and black level measurement
 Auto exposure support by brightness measurement in 5×5 sub windows
 Defect pixel cluster correction unit (DPCC) supports on the fly and table based pixel correction
 De-noising pre filter (DPF)  Enhanced color interpolation (RGB Bayer demosaicdemosaic demosaic demosaicdemosaicdemosaic)
 Chromatic aberration correction
 Combined edge sensitive Sharpening / Blurring filter (Noise filter)
 Color correction matrix (cross talk matrix)
 Image Stabilization support and Video Stabilization Measurement
 Flexible Histogram calculation
 Digital image effects (Emboss, Sketch, Sepia, B/W (Grayscale), Color Selection, Negative image, sharpening)
 Solarize effect through gamma correction
 AXI 64 bit interface 32Bit Address range (two DMA-write ports and one DMA-read port)
 Up to 16 Beat Bursts depending on configured FIFO size
 32 bit AHB programming interface
 Maximum input resolution of 3264×2448 pixels
 Main scaler with pixel-accurate up- and down-scaling to any resolution between 3264×2448 and 32×16 pixel in processing mode
 Self scaler with pixel-accurate up- and down-scaling to any resolution between 1920×1080 and 32×16 pixel in processing mode
 Support of semiplanar NV21 color storage format
 Support of image cropping
 Support Y12BIT and UV 8BIT path output after GAMMAOUT module
 Support RGB output after GAMMAOUT module
 Support hurry for latency FIFO
 Support Two-in-one RK-Tone-Mapping with wide dynamic range unit (Block/Global WDR)
 Support Video Stabilization Measurement (VSM) Programming update to 3264×2448
 CIF
 Support YCbCr422 input
 Support Raw 8bit input
 Support CCIR656(PAL/NTSC) input
 Support 1/2/4 channels mixed data of CCIR656 input
 Support JPEG input
 Support YCbCr422/420 output
 Support UYVY/VYUY/YUYV/YVYU configurable
 Support up to 8192×8192 resolution source
 Support picture in picture
 Support arbitrary size window crop
 Support error/terminate interrupt and combined interrupt output
 Support CLK/VSYNC/HREF polarity configurable
 Support one frame stop/ping-pong mode
 TV DECODER
 Support formats
 PAL
 NTSC
 NTSC or PAL standard is automatically selected depending on the detected input line standard
 Support auto gain control
 VADC
 Sample frequency up to 54MHz
 Support 2’s complement 10bit output
 The gain of programmable amplifier can be adjusted from 0.5 to 2
 Support internal buffer circuit
 Support low pass filter
1.1.8 Video CODEC
 Video Decoder
 Real-time video decoder of H.264
 Supports frame timeout interrupt , frame finish interrupt and bit stream error interrupt
 Error detection and concealment support for all video formats
 Output data format YUV420 semi-planar,YUV400(monochrome) ,YUV422 is supported by H.264
 H.264 8bit up to HP level 5.0 : 1440p@30fps (2560×1440)
 Video Encoder
 Support video encoder for H.264 UP to HP@level4.2
 Only support I and P slices ,not B slices
 Support CBR and VBR
 Support 8-area OSD insertion
 Support Link table configuration for high frame rate application
 Support ROI
 Support Slice split
 Support Low latency encoding
 Support Color domain conversion
 Support Cropping and mirror
 Support De-noise and enhancement
 Input data format:
 YCbCr 4:2:0 planar
 YCbCr 4:2:0 semi-planar
 YCbCr 4:2:2 planar
 YCbCr 4:2:2 semi-planar
 YCbYCr 4:2:2 interleaved
 YCbCr 4:4:4 planar
 YCbCr 4:4:4 semi-planar
 RBG565
 RBG888
 ARBG8888
 Output Bit stream of H.264 “slice_layer_without_partitioning_rbsp()”
 Output ME results(SAD and MV) for each 16×16 block (optional)
 Image size is from 128×128 to 4096×2304
 Maximum frame rate is up to 2560×1440@30fps + 1280×720@30fps
1.1.9 JPEG CODEC
 JPEG codec
 Input JPEG file : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4 sampling formats
 Output raw image : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4 semi-planar
 Support decode and encode from 48×48 to 8176×8176(66.8Mpixels), step size 8 pixels
 Support JPEG ROI(region of image) decode
 Maximum data rate③ is up to 76million pixels per second
1.1.10 Image Enhancement (IEP module)
 Image format support
 Input data: YUV420/YUV422
 Output data: YUV420/YUV422
 YUV swap
 UV SP/P
 BT601_l/BT601_f/BT709_l/BT709_f color space conversion
 YUV up/down sampling
 De-interlace
 3×5 Y motion detection matrix
 Source width up to 720×576, 720×480
 Configured high frequency de-interlace
 I4O2 (Input 4 field, output 2 frame) /I4O1B/I4O1T/I2O1B/I2O1T mode
 Interface
 32bit AHB bus slave
 64bit AXI bus master
 Combined interrupt output
1.1.11 Graphics Engine
 2D Graphics Engine(RGA module) :
 Source formats :
 ABGR8888, XBGR888, ARGB8888, XRGB888
 RGB888, RGB565
 RGBA5551, RGBA4444
 YUV420 planar, YUV420 semi-planar
 YUV422 planar, YUV422 semi-planar
 YUV 10-bit for YUV420/422 semi-planar
 BPP8, BPP4, BPP2, BPP1
 Destination formats :
 ABGR8888, XBGR888, ARGB8888, XRGB888
 RGB888, RGB565
 RGBA5551, RGBA4444
 YUV420 planar, YUV420 semi-planar
 YUV422 planar, YUV422 semi-planar
 Pixel Format conversion, BT.601/BT.709
 Max resolution: 8192×8192 source, 4096×4096 destination
 BitBLT
 Two source BitBLT:
 A+B=B only BitBLT, A support rotate & scale when B fixed
 A+B=C second source (B) has same attribute with (C) plus rotation function
 Color fill with gradient fill, and pattern fill
 High-performance stretch and shrink
 Monochrome expansion for text rendering
 New comprehensive per-pixel alpha(color/alpha channel separately)
 Alpha blending modes including Java 2 Porter-Duff compositing blending rules , chroma key, pattern mask, fading
 Dither operation
 0, 90, 180, 270 degree rotation
 x-mirror, y-mirror & rotation operation
1.1.12 Video OUT
 Display Interface
 Support HDMI 1.4 output up to 1080p@60Hz
 TV Interface: TV encoder 10bit out for DAC
 HDMI Interface : 24 bit(RGB888 YCbCr444),
 Max output resolution 1080p for HDMI,720p for MIPI, 480i/576i for CVBS
 Display process
 Background layer: programmable 24-bit color
 Win0 layer
 RGB888, ARGB888, RGB565, YCbCr422, YCbCr420, YCbCr444
 RB/alpha/mid/uv swap
 1/8 to 8 scaling-down and scaling-up engine
 Support virtual display
 256 level alpha blending (pre-multiplied alpha support)
 Transparency color key
 De-flicker support for interlace output
 YCbCr2RGB(rec601-mpeg/ rec601-jpeg/rec709)
 RGB2YCbCr(BT601/BT709)
 Win1 layer
 RGB888, ARGB888, RGB565
 RB/alpha/endian swap
 Support virtual display
 256 level alpha blending (pre-multiplied alpha support)
 Transparency color key
 Direct path support
 RGB2YCbCr(BT601/BT709)
 Others
 Win0 layer and Win1 layer overlay exchangeable
 BCSH(Brightness, Contrast, Saturation, Hue adjustment)
 BCSH:YCbCr2RGB(rec601-mpeg/ rec601-jpeg/rec709)
 BCSH:RGB2YCbCr(BT601/BT709)
 Support Gamma adjust for PAD
 Support dither down allegro RGB888to666 RGB888to565 & dither down frc (configurable ) RGB888to666
 Blank and black display
 Standby mode
 Support RB/RG/BG/delta/dummy swap

1.1.13 HDMI
 Support RGB888 1080p @ 60fps
 HPD input analog comparator
 Compliance HDMI compliance Test specification 1.4
 Support multi-channels PCM or compressed audio transmission (32-192kHz Fs) from I2S, using IEC60958 and IEC 61937
1.1.14 MIPI DSI
 Support RGB888 720p @ 60fps
 Support 4 lanes
 Support command mode
 Compliance MIPI Alliance Standard for Display Pixel Interface (DPI-2)
1.1.15 Audio Interface
 I2S0 with 8ch
 I2S0 supports up to 8 channels (8xTX, 8xRX)
 Audio resolution from 16bits to 32bits
 Sample rate up to 192KHz
 Provides master and slave work mode, software configurable
 Support 3 I2S formats (normal, left-justified, right-justified)
 Support 4 PCM formats(early, late1, late2, late3)
 I2S and PCM mode cannot be used at the same time
 I2S1/I2S2(PCM) with 2ch
 Up to 2 channels (2xTX, 2xRX)
 Audio resolution from 16bits to 32bits
 Sample rate up to 192KHz
 Provides master and slave work mode, software configurable
 Support 3 I2S formats (normal , left-justified , right-justified)
 Support 4 PCM formats(early , late1 , late2 , late3)
 I2S and PCM cannot be used at the same time
 I2S1 is connected to HDMI and internal Audio Codec
 I2S2 is exposed for peripherals
 Audio CODEC
 24bit DAC
 Support Line-out
 Support Mono, Stereo, 5.1 HiFi channel performance
 Integrated digital interpolation and decimation filter.
 Sampling rate of 8kHz/12kHz/16kHz/24kHz/32kHz/44.1KHz/48KHz/96KHz
 Optional fractional PLL available that support 6MHz to 20MHz clock input to any clock
 Support PCM/I2S Mode
 Support MIC single-ended/double-ended difference input
1.1.16 Connectivity
 SDIO interface
 Compatible with SDIO 3.0 protocol
 4bits data bus widths
 MAC 10/100M Ethernet Controller
 Supports 10/100-Mbps data transfer rates with the RMII interfaces
 Supports both full-duplex and half-duplex operation
 Supports CSMA/CD Protocol for half-duplex operation
 Supports IEEE 802.3x flow control for full-duplex operation
 Optional forwarding of received pause control frames to the user application in full-duplex operation
 Back-pressure support for half-duplex operation
 Automatic transmission of zero-quanta pause frame on de-assertion of flow control input in full-duplex operation
 Preamble and start-of-frame data (SFD) insertion in Transmit, and deletion in Receive paths
 Automatic CRC and pad generation controllable on a per-frame basis
 Options for Automatic Pad/CRC Stripping on receive frames
 Programmable Inter-Frame-Gap (40-96 bit times in steps of 8)
 Supports a variety of flexible address filtering modes
 Separate 32-bit status returned for transmission and reception packets
 Supports IEEE 802.1Q VLAN tag detection for reception frames
 Support detection of LAN wake-up frames and AMD Magic Packet frames
 Support checksum off-load for received IPv4 and TCP packets encapsulated by the Ethernet frame
 Support checking IPv4 header checksum and TCP, UDP, or ICMP checksum encapsulated in IPv4 or IPv6 datagram
 Comprehensive status reporting for normal operation and transfers with errors
 Automatic generation of PAUSE frame control or backpressure signal to the GMAC core based on Receive FIFO-fill (threshold configurable) level
 Handles automatic retransmission of Collision frames for transmission
 Discards frames on late collision, excessive collisions, excessive deferral and under-run conditions
 SPI Controller
 Support serial-master and serial-slave mode, software-configurable
 DMA-based or interrupt-based operation
 Embedded two 32x16bits FIFO for TX and RX operation respectively
 Support 2 chip-selects output in serial-master mode
 SFC
 Support one chip select
 Support x1,x2,x4 data bits mode
 Support interrupt output, interrupt maskable
 Support Spansion, MXIC, Gigadevice …vendor’s nor flash memory.
 UART Controller
 3 on-chip UART controller inside RV1108
 DMA-based or interrupt-based operation
 UART1/1/2 Embedded two 64Bytes FIFO for TX and RX operation respectively
 Support 5bit,6bit,7bit,8bit serial data transmit or receive
 Standard asynchronous communication bits such as start, stop and parity
 Support different input clock for UART operation to get up to 4Mbps or other special baud rate
 Support non-integer clock divides for baud clock generation
 Support auto flow control mode
 I2C controller
 4 on-chip I2C controller in RV1108
 Multi-master I2C operation
 Support 7bits and 10bits address mode
 Software programmable clock frequency and transfer rate up to 400Kbit/s in the fast mode
 Serial 8bits oriented and bidirectional data transfers can be made at up to 100Kbit/s in the standard mode
 GPIO
 4 groups of GPIO (GPIO0~GPIO3) , 32 GPIOs per group in GPIO0~GPIO3, totally have 128 GPIOs
 All of GPIOs can be used to generate interrupt to Cortex-A7
 All of pull-up GPIOs are software-programmable for pull-up resistor or not
 All of pull-down GPIOs are software-programmable for pull-down resistor
 or not
 All of GPIOs are always in input direction in default after power-on-reset
 USB Host2.0
 Embedded 3 USB Host 2.0 interfaces
 Compatible with USB Host2.0 specification
 Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
 Provides 16 host mode channels
 Support periodic out channel in host mode
 USB OTG2.0
 Compatible with USB OTG2.0 specification
 Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
 Support up to 9 device mode endpoints in addition to control endpoint 0
 Support up to 6 device mode IN endpoints including control endpoint 0
 Endpoints 1/3/5/7 can be used only as data IN endpoint
 Endpoints 2/4/6 can be used only as data OUT endpoint
 Endpoints 8/9 can be used as data OUT and IN endpoint
 Provides 9 host mode channels
1.1.17 Others
 Temperature Sensor(TS-ADC)
 10-bits ADC up to 50KS/s sampling rate
 -40~125℃ temperature range and 5℃ temperature resolution
 Successive Approximation ADC (SARADC)
 10-bit resolution
 Up to 1MS/s sampling rate
 6 single-ended input channels
 Current consumption: 0.5mA @ 1MS/s
 eFuse
 Two high-density electrical Fuse is integrated: two 256bits (32×8)
 Support standby mode
 Provide inactive mode, VP must be 0V or Floating in this mode.
 Package Type
 BGA359 (body: 14mm x 14mm; ball size: 0.3mm; ball pitch: 0.65mm)
 RV1108G embedded 128M DDR3-1600.

RV1108 Datasheet Rev 1.5